Abstract: A method and system for emulating a hardware Internet Small Computer System Interface (iSCSI) Host Bus Adapter (HBA) without risking an interruption of communication between a computer and a remote secondary storage device is presented. During normal operations, a (hardware emulating) software iSCSI HBA drives a Network Interface Card (NIC) to afford communication between the computer and the remote secondary storage. If an operating system (OS) anomaly occurs in the computer, the NIC is normally disconnected by the OS. To maintain communication between the computer and the secondary storage device if such an event occurs, a failover network device is called up by the computer's System Management Memory (SMM) Basic Input Output System (BIOS), which allows uninterrupted communication to continue between the computer and remote secondary storage device.

Abstract: A wireless USB hub for connecting a plurality of remote peripheral devices to a computer for communication therewith without the need to physically connect the peripheral devices to the hub via a cable connection. The wireless USB hub includes a receiver for receiving wireless data transmissions from one or more remote peripheral devices. The wireless USB hub further includes a hub controller for passing appropriate peripheral device information to a USB upstream port and then to a computer.

Abstract: An exclusion controller which allows an information processing unit to acquire a contended resource to the exclusion of the other information processing units includes a plurality of non-prioritized information processing units mutually exclusively acquiring a non-prioritized exclusion right, which indicates a candidate for acquiring the contended resource, by a first process. The exclusion controller further includes a prioritized information processing unit acquiring the contended resource by a second process, which requires a shorter processing time than the first process, to the exclusion of the non-prioritized information processing unit having acquired the non-prioritized exclusion right.

Abstract: In an environment in which plural external storage devices having different function control interfaces are intermixed, when a function of a storage device is controlled from a computer, a common interface for controlling the function of the storage device is provided. A device that provides the common interface manages an interrelationship between a storage area recognized by a host computer and a storage area provided by the storage device and associates a storage area which becomes a target of a function control instruction with the storage device that provides the storage area. A type of the storage device that provides the storage area which becomes the target of the function control instruction is identified and function control is ordered through a function control interface unique to the device.

Abstract: A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors through the memory modules in the first rank. The data bandwidth between the processors and the memory modules in the second rank is varied by varying the number of memory modules in the first rank that are used to access the memory module in the second set. Each of the memory modules includes several memory devices coupled to a memory hub. The memory hub includes a memory controller coupled to each memory device, a link interface coupled to a respective processor or memory module, and a cross bar switch coupling any of the memory controllers to any of the link interfaces.

Abstract: A communication apparatus includes a radio frequency circuit that operates on a radio frequency signal and a digital processing circuit coupled to the radio frequency circuit. The digital processing circuit includes a plurality of bus masters coupled to a shared bus. A bus arbiter is provided for arbitrating between requests to access the bus by a first bus master and one or more other bus masters. Accesses by the one or more other bus masters to the bus are restricted in response to a signal indicative of a change in a mode of operation of the RF circuit. In one particular implementation, a communication apparatus employs time domain isolation wherein the digital processing circuit may be placed in a shutdown mode when the radio frequency circuit is active.

Abstract: A wireless USB hub for connecting a plurality of remote peripheral devices to a computer for communication therewith without the need to physically connect the peripheral devices to the hub via a cable connection. The wireless USB hub includes a receiver for receiving wireless data transmissions from one or more remote peripheral devices. The wireless USB hub further includes a hub controller for passing appropriate peripheral device information to a USB upstream port and then to a computer.

Abstract: In a virtual computing machine, a system and method that dynamically patches the interrupt mechanism (in interrupt vector space) of a host computing architecture with guest mode software. Significant increases in performance are achieved without depending on the host code. A patching mechanism evaluates the operating system version, processor, and code to be patched. If patchable, low-level interfaces are created dynamically; a dispatcher is written into an unused location in vector space, and instructions copied from each interrupt vector to be patched to a guest interrupt vector. For an interrupt, the new, patched instructions branch to the dispatcher, which then branches to the appropriate patched interrupt guest code. If the processor is operating as a virtual machine, the guest interrupt code handles the interrupt, otherwise the original copied instructions are replayed, followed by execution at the original host instruction in vector space that exists after the copied and patched instructions.

Abstract: An apparatus, system, and method enable access to a storage system by distinguishing SCSI Object-Based Storage Device Commands (OSD) commands from Fibre Channel (FC) SCSI commands on the same port and storage subsystem. The storage subsystem has the capability of identifying the storage protocol from a corresponding command, and processes the command accordingly for a storage device formatted for use with the respective storage protocol. This way, a storage subsystem can consolidate data from several dedicated command ports to a single physical port, while also enabling a single storage system to store and provide access to data in multiple different storage protocol formats.

Abstract: When the capacity availability of buffer memory provided to an output port of a frame to be transferred is exceeding a predetermined value, a crossbar switch is used for path change of the frame. When the capacity availability of the buffer memory of the output port is the predetermined value or lower, the frame is written into shared memory. Then, the frame is read from the shared memory for transfer to the output port. By selectively performing frame transfer using the crossbar switch and frame transfer via the shared memory, the effects can be reduced even if the port buffer overflows, and the writing throughput can be favorably improved.

Abstract: A method and apparatus is presented that can provide first and second windows for driving data onto a bus in dependence on bus clock frequency. In one example, the speed of the bus clock is determined by a component such as a processor. If the bus clock frequency is at a first, relatively high frequency, data is driven onto the bus in an earlier time window (e.g., near the rising edge of the bus clock signal). If the bus clock frequency is at a second, lower frequency, data is driven onto the bus in a second, later time window (e.g., near the center of the high level of the bus clock). Accordingly, the time window for receiving the data driven onto the bus need not be changed (e.g., near the rising edge of the next bus clock signal) allowing components to work effectively with both bus clock frequencies.

Abstract: A system includes a bus shared by a plurality of devices and a logic circuit adapted to segment the bus into a plurality of portions. In one embodiment of the present invention, the system may include a plurality of devices and a first multiplexer logic circuit adapted to select signals from the plurality of devices. A second multiplexer circuit may receive the selected signals from the first multiplexer circuit and transmit the selected signals to chosen ones of the plurality of devices.

Abstract: Bandwidth information including a plurality of slots each having highest priority order information for arbitrating access conflict, and priority master information for specifying, as a priority master, one or more of a plurality of masters whose latency in accessing a memory serving as a shared resource is desired to be reduced are included as arbitration information. When an arbitration section arbitrates access conflict while switching the slots in the bandwidth information at each of predetermined arbitration timings, if there is an access request from the priority master specified in the priority master information, the arbitration section changes the sequence of the slots in the bandwidth information so as to allow the priority master to access the memory with priority.

Abstract: In one embodiment, the present invention includes a method for sending a connection request from a requestor endpoint to a target endpoint based on route information stored in the requestor endpoint, and receiving a connection confirmation from the target endpoint to confirm establishment of a peer-to-peer connection between the endpoints. The endpoints may be part of an Advanced Switching (AS) for Peripheral Component Interconnect (PCI) Express™ architecture, and in one embodiment a simple load store (SLS) protocol may be used for peer-to-peer communications in the AS environment. Other embodiments are described and claimed.

Abstract: An adaptive weighted arbitration algorithm that is user configurable is discussed. The arbitration logic and algorithm considers past arbitration history events and is dynamic to allow for losing bidders to increase their probability of being selected to access the resource based on an accumulator value and a weight value.

Abstract: A low-latency, peer-to-peer TDM bus including one or more data lines and one or more control lines is provided. Attached devices access the bus sequentially in order of their bus addresses. During a device's access period, if the device has data to transmit, the device places its address on the data lines, asserts a START signal on the bus, and proceeds to transmit data to the other devices on the bus. When the data transmission is completed, the device asserts an END signal on the bus, thus passing control of the bus to the next device in the sequence. If the device has no data to transmit, the device simply places its address on the data lines, asserts the START signal, and asserts the END signal, and control passes directly to the next device in line. In this manner, each device has an opportunity to transmit on the bus.

Abstract: The present invention provides systems, methods, and bus controllers (12) for monitoring an event of interest via a network bus (14) and creating an asynchronous event trigger on the network bus indicating that the event occurred. Importantly, the systems, methods, and bus controllers (12) of the present invention use either one or several network devices (16, 18) that are connected to the network bus (14) and monitor the occurrence of an event of interest. These network devices (16, 18) are configure through commands from the bus controller (12) to indicate on the network bus (14) typically by a pulse signal, when the event of interest has occurred. The indication from the network device (16, 18) that the event has occurred is used by the bus controller (12) and other network devices (16, 18, 20) on the network bus (14) to configure timing for commands or to perform desired actions in synchronization with the occurrence of the event of interest.

Abstract: Embodiments of the invention include a bus bridge that is capable of communicating with more than one MSC device coupled to it. In some embodiments, the bridge includes a LUN processor that translates different LUN numbers received from the bus into different addresses and LUNs for devices connected to the bridge. The bridge masks the fact that multiple MSC devices are coupled to it by reporting to the host that only a single device having multiple LUNs are coupled to the bridge.

Abstract: A peripheral for notifying a USB-connected upper apparatus of a device descriptor and allowing the upper apparatus to specify a communication partner destination by the function information shown in the device descriptor has: a peripheral function information holding unit which holds function information showing functions of the peripheral; a dependent peripheral function information holding unit which holds function information showing functions of a USB-connected dependent peripheral; and a USB control unit which reads out one of the function information held in those holding units by a selecting instruction and notifies the upper apparatus of the device descriptor in which the read-out function information is shown. A peripheral which can realize a multi-function without developing a dedicated driver and installing it into a PC is provided.

Abstract: The systems and methods manage concurrent access requests to a shared resource. The systems and methods utilize an access management algorithm that permits multiple processes to concurrently obtain shared locks on the shared resource, but also limits access to only one process when an exclusive lock is granted. In doing so, the systems and methods avoid the problems of starvation and deadlock.