Abstract: Among multiple drain regions, a contact surface area between second contacts and a drain region most proximal to a central portion of an element region in a second direction is less than a contact surface area between second contacts and a drain region disposed on an outermost side of the element region in the second direction. The multiple drain regions are arranged in the second direction.

Abstract: An integrated circuit includes a T-coil circuit, a silicon-controlled rectifier (SCR), and a signal-loss prevention circuit. The T-coil circuit is coupled to an input/output (I/O) pad and an internal circuit. The SCR is coupled to the T-coil circuit and the internal circuit. The signal-loss prevention circuit is coupled to the T-coil circuit and the SCR. The signal-loss prevention circuit includes a resistor coupled to the T-coil circuit and the SCR. An electrostatic current flows through the resistor and turns on the SCR. The signal-loss prevention circuit may also include a diode circuit coupled to the T-coil circuit and the SCR. The diode circuit is configured to prevent signal loss.

Abstract: A silicon on insulator (SOI) device includes a wafer and a trap-rich layer. The wafer includes a top silicon layer disposed on a buried oxide layer. The trap-rich layer having nano-dots and an oxide layer are stacked on a high resistivity substrate sequentially, wherein the oxide layer is bonded with the buried oxide layer. Or, a silicon on insulator (SOI) device includes a wafer and a high resistivity substrate. The wafer includes a top silicon layer disposed on a buried oxide layer. The high resistivity substrate is bonded with the buried oxide layer, wherein a positive fixed charge layer is induced at a surface of the buried oxide layer contacting the high resistivity substrate, and a doped negative charge layer is right next to the positive fixed charge layer. The present invention also provides a method of forming said silicon on insulator (SOI) device.

Abstract: Aspects of the disclosure provide a method for fabricating semiconductor device. The method includes characterizing an etch process that is used to etch channel holes and dummy channel holes in a stack of alternating sacrificial gate layers and insulating layers upon a substrate of a semiconductor device. The channel holes are in a core region and the dummy channel holes are in a staircase region. The stack of alternating sacrificial gate layers and insulating layers extend from the core region into in the staircase region of a stair-step form. The method further includes determining a first shape for defining the dummy channel holes in a layout based on the characterization of the etch process. The first shape is different from a second shape for defining the channel holes.

Abstract: The embodiments herein describe a vertical field effect transistor (FET) with a gate that includes different work function metals (WFMs). Each WFM can be made up of one material (or one layer) or multiple materials forming multiple layers. In any case, the gate includes at least two different WFMs. For example, a first WFM may have a different material or layer than a second WFM in the gate, or one layer of the first WFM may have a different thickness than a corresponding layer in the second WFM. Having different WFMs in the gate can reduce the gate induced drain leakage (GIDL) in the FET.

Abstract: The present disclosure describes a method for the formation of gate-all-around nano-sheet FETs with tunable performance. The method includes disposing a first and a second vertical structure with different widths over a substrate, where the first and the second vertical structures have a top portion comprising a multilayer nano-sheet stack with alternating first and second nano-sheet layers. The method also includes disposing a sacrificial gate structure over the top portion of the first and second vertical structures; depositing an isolation layer over the first and second vertical structures so that the isolation layer surrounds a sidewall of the sacrificial gate structure; etching the sacrificial gate structure to expose each multilayer nano-sheet stack from the first and second vertical structures; removing the second nano-sheet layers from each exposed multilayer nano-sheet stack to form suspended first nano-sheet layers; forming a metal gate structure to surround the suspended first nano-sheet layers.

Abstract: An LED wafer includes LED dies on an LED substrate. The LED wafer and a carrier wafer are joined. The LED wafer that is joined to the carrier wafer is shaped. Wavelength conversion material is applied to the LED wafer that is shaped. Singulation is performed to provide LED dies that are joined to a carrier die. The singulated devices may be mounted in an LED fixture to provide high light output per unit area.

Abstract: An organic light-emitting display device comprises a substrate, a driving thin-film transistor including an active layer on the substrate, source and drain electrodes directly contacting the active layer, and a gate electrode on the active layer, and an organic light-emitting element connected to the driving thin-film transistor. Each of the source and drain electrodes of the driving thin-film transistor exposes a respective side surface of the active layer.

Abstract: A semiconductor capacitor array layout includes a first conductive structure and a second conductive structure. The first conductive structure includes: longitudinal first conductive strips in a first integrated circuit (IC) layer; and lateral first conductive strips that are in a second IC layer and coupled to the longitudinal first conductive strips. The longitudinal and lateral first conductive strips jointly form well-shaped structures including outer wells and inner wells. The outer wells are not electrically coupled to the inner wells. The second conductive structure includes second conductors that are respectively disposed in the well-shaped structures in the first IC layer. The second conductors include outer second conductors respectively positioned in the outer wells and inner second conductors respectively positioned in the inner wells. The outer second conductor are not electrically coupled to the inner second conductor.

Abstract: An ESD protection device (100) is disclosed. More particularly, the ESD protection device is configured so that a gate electrode (140) and a capacitor electrode (170) electrically connected to a drain region (162) are spaced apart from each other by a preset distance, and partially or entirely overlap each other, thereby increasing a capacitance (Cgd) between the gate electrode and the drain region.

Abstract: Aspects of the disclosure provide methods for manufacturing semiconductor devices. One of the methods forms a string of transistors in a semiconductor device over a substrate of the semiconductor device. The method includes forming a first substring of transistors having a first channel structure that includes a first channel layer and a first gate dielectric structure that extend along a vertical direction over the substrate. The method includes forming a channel connector over the first substring and forming the second substring above the channel connector. The second substring has a second channel structure. The second channel structure includes the second channel layer and a second gate dielectric structure that extend along the vertical direction. The second gate dielectric structure is formed above the channel connector. The channel connector electrically couples the first channel layer and the second channel layer.

Abstract: A semiconductor device includes: a drift layer of a first conduction type provided in a semiconductor substrate having a first principal plane and a second principal plane opposed to the first principal plane; a first semiconductor layer of a second conduction type provided between the first principal plane of the semiconductor substrate and the drift layer and having impurity concentration higher than impurity concentration of the drift layer; a first buffer layer of a first conduction type provided between the second principal plane of the semiconductor substrate and the drift layer and having hydrogen-induced donors with impurity concentration higher than impurity concentration of the drift layer; and a second semiconductor layer of a first conduction type or a second conduction type provided between the second principal plane of the semiconductor substrate and the first buffer layer and having impurity concentration higher than impurity concentration of the drift layer, wherein the first buffer layer incl

Abstract: A quantum dot device includes: a first electrode and a second electrode facing each other; a quantum dot layer between the first electrode and the second electrode, and an electron auxiliary layer between the quantum dot layer and the second electrode, the electron auxiliary layer including a first nanoparticle and a second nanoparticle which is larger than the first nanoparticle, wherein a work function of the first electrode is greater than a work function of the second electrode, and wherein a difference between a lowest unoccupied molecular orbital energy level of the quantum dot layer and a lowest unoccupied molecular orbital energy level of the electron auxiliary layer is less than about 1.1 electronvolts.

Abstract: Three-dimensional integrated circuit structures are disclosed. A three-dimensional integrated circuit structure includes a first die, a second die and a device-free die. The first die includes a first device. The second die includes a second device and is bonded to the first die. The device-free die is located aside the second die and is bonded to the first die. The device-free die includes a conductive feature electrically connected to the first die and the second die.

Abstract: A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.

Abstract: A semiconductor device structure and a method for fabricating the same. The semiconductor device structure includes an embedded memory device and an electrode in contact with a top surface of the memory embedded device. A metal encapsulation layer is in contact with a top surface of the electrode and a portion of sidewalls of the electrode. The metal encapsulation layer comprises one or more materials that are chemical etch resistant and are conductive when oxidized. The method includes forming an insulating layer over a memory device and an electrode in contact with the memory device. Portions of the insulating layer are etched. The etching exposes a top surface and a portion of sidewalls of the electrode. A metal encapsulation layer is formed over and in contact with the top surface and the portion of sidewalls of the electrode.

Abstract: A semiconductor device and method of forming the same are disclosed. The semiconductor device includes a substrate, an isolation structure over the substrate, a fin extending from the substrate, and an epitaxial feature over the fin. The epitaxial feature comprises a lower portion and an upper portion. The lower portion extends from the fin and extends above the isolation structure. The upper portion is over the lower portion. The upper portion extends partially through the lower portion in a cross section perpendicular to a lengthwise direction of the fin.

Abstract: A lateral transistor having a well region, a body region, a source region, a drain region, a gate structure and a trenched Schottky barrier structure. The trenched Schottky barrier structure extended vertically from a top surface of the well region through the source region and the body region and penetrated into at least a portion of the well region to form a vertical Schottky contact.

Abstract: The present disclosure provides embodiments of semiconductor structures. A semiconductor structure according to the present disclosure includes a substrate, a fin-shaped structure disposed over the substrate, the fin-shaped structure including a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers, a gate structure disposed over a channel region of the fin-shaped structure, a first source/drain feature extending through at least a first portion the fin-shaped structure, a second source/drain feature extending through at least a second portion of the fin-shaped structure, and a backside metal line disposed below the substrate and spaced apart from the first source/drain feature and the second source/drain feature.

Abstract: An ESD protection device (100) is disclosed. More particularly, the ESD protection device is configured so that a gate electrode (140) and a capacitor electrode (170) electrically connected to a drain region (162) are spaced apart from each other by a preset distance, and partially or entirely overlap each other, thereby increasing a capacitance (Cgd) between the gate electrode and the drain region.