Patents Examined by Mark Hatzilambrou
  • Patent number: 11177239
    Abstract: A semiconductor device including control switches enabling a semiconductor die in a stack of semiconductor die to send or receive a signal, while electrically isolating the remaining die in the die stack. Parasitic pin cap is reduced or avoided by electrically isolating the non-enabled semiconductor die in the die stack.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: November 16, 2021
    Assignee: SanDisk Information Technology (Shanghai) Co., Ltd.
    Inventors: Shineng Ma, Chin-Tien Chiu, Chih-Chin Liao, Ye Bai, Yazhou Zhang, Yanwen Bai, Yangming Liu
  • Patent number: 11075295
    Abstract: A metal-oxide-semiconductor field-effect transistor includes a wide bandgap substrate, a wide bandgap drift layer over the substrate, a number of junction implants in the drift layer, and a JFET region between the junction implants. The JFET region is defined by a JFET gap, which is the distance between adjacent ones of the junction implants. The JFET gap is not uniform throughout the MOSFET device. The JFET region is separated into a first JFET sub-region and a second JFET sub-region, such that a doping concentration in the first JFET sub-region is different from a doping concentration in the second JFET sub-region.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: July 27, 2021
    Assignee: Cree, Inc.
    Inventor: Sei-Hyung Ryu
  • Patent number: 11031395
    Abstract: The present disclosure describes a method for the formation of gate-all-around nano-sheet FETs with tunable performance. The method includes disposing a first and a second vertical structure with different widths over a substrate, where the first and the second vertical structures have a top portion comprising a multilayer nano-sheet stack with alternating first and second nano-sheet layers. The method also includes disposing a sacrificial gate structure over the top portion of the first and second vertical structures; depositing an isolation layer over the first and second vertical structures so that the isolation layer surrounds a sidewall of the sacrificial gate structure; etching the sacrificial gate structure to expose each multilayer nano-sheet stack from the first and second vertical structures; removing the second nano-sheet layers from each exposed multilayer nano-sheet stack to form suspended first nano-sheet layers; forming a metal gate structure to surround the suspended first nano-sheet layers.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tetsu Ohtou, Ching-Wei Tsai, Jiun-Jia Huang, Kuan-Lun Cheng, Chi-Hsing Hsu
  • Patent number: 10930777
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an LDMOS device on FDSOI structures and methods of manufacture. The laterally double diffused semiconductor device includes a gate dielectric composed of a buried insulator material of a semiconductor on insulator (SOI) technology, a channel region composed of semiconductor material of the SOI technology and source/drain regions on a front side of the buried insulator material such that a gate is formed on a back side of the buried insulator material. The gate terminal can also be placed at a hybrid section used as a back-gate voltage to control the channel and the drift region of the device.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: February 23, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Ignasi Cortes Mayol, Alban Zaka, Tom Herrmann, El Mehdi Bazizi
  • Patent number: 10923582
    Abstract: A semiconductor device is disclosed having a plurality of gate trenches formed on the surface thereof, each filled with a gate insulating film and a gate electrode. A transistor region is defined between adjacent gate trenches forming a pair, and includes an n+-type emitter region, a p-type base region, and an n?-type drift region disposed lateral to each gate trench in the pair, in order in a depth direction of the gate trench from a front surface side of the semiconductor layer. A p+-type collector region disposed on a back surface side of the semiconductor layer with respect to the n?-type drift region. A plurality of emitter trenches are formed one either side of each of the gate trenches in the pair of gate trenches.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: February 16, 2021
    Assignee: ROHM CO., LTD.
    Inventor: Akihiro Hikasa
  • Patent number: 10886277
    Abstract: A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: January 5, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Augustin Jinwoo Hong, Young-Ju Lee, Joon-Yong Choe, Jung-Hyun Kim, Sang-Jun Lee, Hyeon-Kyu Lee, Yoon-Chul Cho, Je-Min Park, Hyo-Dong Ban
  • Patent number: 10854584
    Abstract: An LED wafer includes LED dies on an LED substrate. The LED wafer and a carrier wafer are joined. The LED wafer that is joined to the carrier wafer is shaped. Wavelength conversion material is applied to the LED wafer that is shaped. Singulation is performed to provide LED dies that are joined to a carrier die. The singulated devices may be mounted in an LED fixture to provide high light output per unit area.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: December 1, 2020
    Assignee: CREE, INC.
    Inventors: Michael John Bergmann, David Todd Emerson, Joseph G. Clark, Christopher P. Hussell
  • Patent number: 10825906
    Abstract: A semiconductor device includes transistor cells and enhancement cells. Each transistor cell includes a body zone that forms a first pn junction with a drift structure. The transistor cells may form, in the body zones, inversion channels when a first control signal exceeds a first threshold. The inversion channels form part of a connection between the drift structure and a first load electrode. A delay unit generates a second control signal which trailing edge is delayed with respect to a trailing edge of the first control signal. The enhancement cells form inversion layers in the drift structure when the second control signal falls below a second threshold lower than the first threshold. The inversion layers are effective as minority charge carrier emitters.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: November 3, 2020
    Assignee: Infineon Technologies AG
    Inventors: Johannes Georg Laven, Roman Baburske, Matteo Dainese, Christian Jaeger
  • Patent number: 10818748
    Abstract: A method for manufacturing a thin film resistor (TFR) module includes forming a TFR element over a substrate; annealing the TFR element to reduce the temperature coefficient of resistance (TCR) of the TFR element; and after forming and annealing the TFR element, forming a pair of conductive TFR heads in contact with the TFR element. By forming the TFR element before the TFR heads, the TFR element may be annealed without affecting the TFR heads, and thus may be formed from various materials with different annealing properties, e.g., SiCCr and SiCr. Thus, the TFR element may be annealed to achieve a near 0 ppm TCR, without affecting the later-formed TFR heads. The TFR module may be formed using a damascene CMP approach and using only a single added mask layer. Further, vertically-extending “ridges” at edges of the TFR element may be removed or eliminated to further improve the TCR performance.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: October 27, 2020
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Yaojian Leng, Bonnie Hamlin, Andrew Taylor, Janet Vanderiet, Justin Sato
  • Patent number: 10811583
    Abstract: Provided is a light emitting device package. The light emitting device package comprises a body, a heat diffusing member, a light emitting diode (LED), and a buffer layer. A cavity with an opened topside is formed in the body. The heat dissipation member is disposed between a bottom surface of the cavity and a lower surface of the body. The LED is disposed on one of an electrode disposed on the bottom surface of the cavity. The buffer layer is disposed between the heat dissipation member and a pad and has a thickness thinner than a thickness of the heat dissipation member.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: October 20, 2020
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Byung Mok Kim, Su Jung Jung, Yu Dong Kim, Gun Kyo Lee
  • Patent number: 10811459
    Abstract: A back-illuminated solid-state imaging device includes a semiconductor substrate, a shift register, and a light-shielding film. The semiconductor substrate includes a light incident surface on the back side and a light receiving portion generating a charge in accordance with light incidence. The shift register is disposed on the side of a light-detective surface opposite to the light incident surface of the semiconductor substrate. The light-shielding film is disposed on the side of the light-detective surface of the semiconductor substrate. The light-shielding film includes an uneven surface opposing the light-detective surface.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: October 20, 2020
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Shin-ichiro Takagi, Kentaro Maeta, Yasuhito Yoneta, Hisanori Suzuki, Masaharu Muramatsu
  • Patent number: 10804323
    Abstract: Memory devices and manufacturing methods thereof are presented. A memory device a substrate and a memory cell having at least one selector and a storage element. The selector includes a well of a first polarity type disposed in the substrate, a region of a second polarity type disposed over the well and in the substrate, and first and second regions of the first polarity type disposed adjacent to the region of the second polarity type. The storage element includes a programmable resistive layer disposed on the region of the second polarity type and an electrode disposed over the programmable resistive layer.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: October 13, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Xuan Anh Tran, Eng Huat Toh, Shyue Seng Tan, Yuan Sun, Elgin Kiok Boone Quek
  • Patent number: 10777625
    Abstract: A display device including a plurality of first electrodes arranged in a display region above a substrate, each of the plurality of first electrodes being in common with n (n is an integer of 2 or more number of light emitting elements, a bank having a recess part and partitioning the n number of light emitting elements with the recess part as a boundary in each of the plurality of first electrodes, a light emitting layer arranged above the plurality of first electrodes throughout the display region, and n groups of second electrodes arranged above the light emitting layer and electrically separated with the recess part as a boundary.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: September 15, 2020
    Assignee: Japan Display Inc.
    Inventors: Yasukazu Kimura, Toshihiro Sato
  • Patent number: 10749038
    Abstract: In one aspect, a method of forming a semiconductor device includes the steps of: forming an alternating series of sacrificial/active layers on a wafer and patterning it into at least one nano device stack; forming a dummy gate on the nano device stack; patterning at least one upper active layer in the nano device stack to remove all but a portion of the at least one upper active layer beneath the dummy gate; forming spacers on opposite sides of the dummy gate covering the at least one upper active layer that has been patterned; forming source and drain regions on opposite sides of the nano device stack, wherein the at least one upper active layer is separated from the source and drain regions by the spacers; and replacing the dummy gate with a replacement gate. A masking process is also provided to tailor the effective device width of select devices.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: August 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xin Miao, Ruilong Xie, Tenko Yamashita
  • Patent number: 10727424
    Abstract: A flexible display device has, in a folding portion, a slit that partitions a second electrode provided in common for a plurality of pixels, between a plurality of display units. In a plan view, in the slit, at least one of an organic insulating film, banks, and an organic layer has a slit, and a bulging portion formed by the organic insulating film and the banks is provided so as to surround each of the partitioned second electrodes.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: July 28, 2020
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tetsunori Tanaka, Takeshi Yaneda
  • Patent number: 10727383
    Abstract: An LED package structure includes a substrate, an electrode layer and an insulating layer in a coplanar arrangement and disposed on the substrate, an LED chip mounted on the electrode layer and the insulating layer, a phosphor sheet covering entirely a top surface of the LED chip, a first translucent layer disposed on a light emitting surface of the phosphor sheet, and a reflective housing covering the side surfaces of the LED chip and the side surfaces of the phosphor sheet. The light emitting surface has a central region and a ring-shaped region surrounding the central region. The first translucent layer covers at least 60% of an area of the ring-shaped region. A refractive index of the first translucent layer is larger than one and is smaller than that of the phosphor sheet. A top surface of the reflective housing is substantially flush with the light emitting surface.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: July 28, 2020
    Assignees: LITE-ON OPTO TECHNOLOGY (CHANGZHOU) CO., LTD., LITE-ON TECHNOLOGY CORPORATION
    Inventors: Yu-Yu Chang, Shih-Chiang Yen, Yi-Hsuan Chen, Chen-Hsiu Lin
  • Patent number: 10720428
    Abstract: A high bandgap Schottky contact layer device and methods for producing same are provided herein. According to one aspect, a high bandgap Schottky contact layer device comprises a substrate, a first Schottky layer over the substrate, the first Schottky layer having a first bandgap, and a second Schottky layer over the first Schottky layer, the second Schottky layer having a second bandgap. The device further comprises a first metal contact over the second Schottky layer and at least one ohmic contact, a portion of which being in direct contact with the substrate. The first bandgap is greater than 1.7 electronvolts (eV). In one embodiment, the second bandgap is also greater than 1.7 eV.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: July 21, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Corey A. Nevers, Sheila K. Hurtt
  • Patent number: 10714525
    Abstract: Methods and apparatus for integrating a CMOS image sensor and an image signal processor (ISP) together using an interposer to form a system in package device module are disclosed. The device module may comprise an interposer with a substrate. An interposer contact is formed within the substrate. A sensor device may be bonded to a surface of the interposer, wherein a sensor contact is bonded to a first end of the interposer contact. An ISP may be connected to the interposer, by bonding an ISP contact in the ISP to a second end of the interposer contact. An underfill layer may fill a gap between the interposer and the ISP. A printed circuit board (PCB) may further be connected to the interposer by way of a solder ball connected to another interposer contact. A thermal interface material may be in contact with the ISP and the PCB.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chung Yee, Chun Hui Yu
  • Patent number: 10714609
    Abstract: A semiconductor device includes a plurality of gate trenches formed in a first surface of a semiconductor body and extending lengthwise parallel to one another, transistor cells and diode regions formed in a mesa of the semiconductor body between neighboring ones of the gate trenches, and a drift region in the semiconductor body beneath the gate trenches. Each transistor cell includes a source zone and a body region. Each diode region includes a contact portion and a lower doped shielding portion. The source zone forms a first p-n junction with the body region, and the body region forms a second p-n junction with the drift region. The contact region extends to the first surface, and the shielding portion forms a third p-n junction with the drift region. The shielding portion extends under bottoms of the neighboring ones of the gate trenches.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: July 14, 2020
    Assignee: Infineon Technologies AG
    Inventors: Thomas Aichinger, Dethard Peters, Ralf Siemieniec
  • Patent number: 10707223
    Abstract: Characteristics of a semiconductor device having a nonvolatile memory are improved. A high dielectric constant film is provided on an insulating film between a memory gate electrode and a fin as components of a nonvolatile memory. The high dielectric constant film is provided over the top of the fin and the top of an element isolation region, but is not provided over a side surface of the fin. In this way, since the high dielectric constant film is provided over the top of the fin and the top of the element isolation region, it is possible to relax an electric field in the vicinity of each of the upper and lower corner portions of the fin, leading to an improvement in disturbance characteristics.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: July 7, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Shunichi Narumi