Abstract: A system for rendering visual images that combines sophisticated anti-aliasing and pixel blending techniques with control pipelining in hardware embodiment. A highly-parallel rendering pipeline performs sophisticated polygon edge interpolation, pixel blending and anti-aliasing rendering operations in hardware. Primitive polygons are transformed to subpixel coordinates and then sliced and diced to create "pixlink" elements mapped to each pixel. An oversized frame buffer memory allows the storage of many pixlinks for each pixel. Z-sorting is avoided through the use of a linked-list data object for each pixlink vector in a pixel stack. Because all image data values for X, Y, Z, R, G, B and pixel coverage A are maintained in the pixlink data object, sophisticated blending operations are possible for anti-aliasing and transparency. Data parallelism in the rendering pipeline overcomes the processor efficiency problem arising from the computation-intensive rendering algorithms used in the system of this invention.
Type:
Grant
Filed:
June 19, 1995
Date of Patent:
February 16, 1999
Assignee:
Nihon Unisys, Ltd.
Inventors:
Roman Kuchkuda, John Rigg, Manuel Rey Enriquez, James V. Henson, Curt Stehley
Abstract: An apparatus for rapidly switching between output display frames using a shared frame identification memory is disclosed which has particular application to high resolution graphics for animation. Through a plurality of comparison circuitry, the apparatus enables a frame to be displayed during the clock cycles when the frame identification memory is read and during the clock cycles when the frame identification memory is provided with input, thereby, allowing a frame identification memory to be shared by two output display memories. As a result the rapid switching between output display frames sufficient for animation may be achieved with less hardware.