Abstract: The present invention relates to a process for preparing silylated polyurethane polymers which have increased stability under ambient condition or storage toward atmospheric moisture, in the presence of at least one of titanium-containing catalyst or zirconium-containing catalyst and to silylated polyurethane polymer compositions comprising these catalysts.

Abstract: The present invention relates to a polysiloxane compound having a structure represented by formula 1: wherein each of F1, F2, F3 and F4 is individually selected from one of a first group, a second group, a third group and a fourth group, the first group is selected from a C2˜C10 hydrocarbon group having amino group(s), a C2˜C10 hydrocarbon group having epoxy group(s), a C2˜C10 hydrocarbon group having carbonyl group(s) or a C2˜C10 hydrocarbon group having alkoxy group(s), the second group is a C2˜C10 hydrocarbon group having amino group(s), the third group is selected from a C2˜C10 hydrocarbon group having epoxy group(s), a C2˜C10 hydrocarbon group having carbonyl group(s), a C2˜C10 hydrocarbon group having SiCl group(s) or a C2˜C10 hydrocarbon group having alkoxy group(s), the fourth group is selected from a C2˜C10 hydrocarbon group having aryl group(s) or a C2˜C10 hydrocarbon group having alkoxy group(s).

Abstract: Polythioether polymers, curable compositions of polythioether polymers, the process of making polythioether polymers, and the use of polythioether polymers in sealants, wherein the polythioether polymers and curable compositions are liquid at a temperature of 20° C. or less, are disclosed.

Abstract: The present invention relates to a method, apparatus and system for managing virtual memory, in which a co-processor (224) is adapted to use virtual memory with a host processor (202). A host memory (203) is coupled to the host processor (202) to implement the virtual memory. The co-processor (224) includes a virtual-physical memory mapping device (915) for interrogating a virtual memory table and for mapping one or more virtual memory addresses (880) requested by the co-processor (224) into corresponding physical addresses (873) in the host memory (203). The virtual memory table is stored in two or more non-contiguously addressable regions of the host memory (203), and is preferably a page table. The memory mapping device (915) further includes a multiple-entry translation lookaside buffer (889) for caching virtual-to-physical address mappings (872), where entries in the buffer (889) are replaced on a least recently used replacement basis.