Abstract: 3D semiconductor device including: a first level including first single-crystal transistors; a plurality of memory control circuits formed from at least a portion of the first single-crystal transistors; a first metal layer disposed atop the first single-crystal transistors; a second metal layer disposed atop the first metal layer, a second level disposed atop the second metal layer includes second transistors and a memory array of first memory cells, a third level including second memory cells which include some third transistors, which themselves include a metal gate and is disposed above the second level; a third metal layer disposed above the third level; a fourth metal layer disposed above the third metal layer, a connective path from the third metal layer to the second metal layer with a thru second level via of a diameter less than 800 nm which also passes thru the memory array, different write voltages for different dies.

Abstract: Among other things, a method of fabricating an integrated electronic device package is described. First trace portions of an electrically conductive trace are formed on an electrically insulating layer of a package structure, and vias of the conductive trace are formed in a sacrificial layer disposed on the electrically insulating layer. The sacrificial layer is removed, and a die is placed above the electrically insulating layer. Molding material is formed around exposed surfaces of the die and exposed surfaces of the vias, and a magnetic structure is formed within the layer of molding material. Second trace portions of the electrically conductive trace are formed above the molding material and the magnetic structure. The electrically conductive trace and the magnetic structure form an inductor. The electrically conductive trace may have a coil shape surrounding the magnetic structure. The die may be positioned between portions of the inductor.

Abstract: A method includes forming a semiconductor fin, forming a gate stack on the semiconductor fin, and a gate spacer on a sidewall of the gate stack. The method further includes recessing the semiconductor fin to form a recess, performing a first epitaxy process to grow a first epitaxy semiconductor layer in the recess, wherein the first epitaxy semiconductor layer, and performing a second epitaxy process to grow an embedded stressor extending into the recess. The embedded stressor has a top portion higher than a top surface of the semiconductor fin, with the top portion having a first sidewall contacting a second sidewall of the gate spacer, and with the sidewall having a bottom end level with the top surface of the semiconductor fin. The embedded spacer has a bottom portion lower than the top surface of the semiconductor fin.

Abstract: A thin film transistor includes a gate electrode, a semiconductor layer overlapped with the gate electrode, a gate insulating layer between the gate electrode and the semiconductor layer, and a source electrode and a drain electrode electrically connected to the semiconductor layer. The semiconductor layer includes a plurality of holes. The gate insulating layer may include a plurality of recess portions at a surface of the gate insulating layer facing the semiconductor layer. A method of manufacturing the thin film transistor is provided. A thin film transistor array panel and an electronic device may include the thin film transistor.

Abstract: The present application provides a splicing display device. The splicing display device includes at least two display devices, a middle frame and a light emitting diode (LED) substrate. Each two adjacent display devices are spliced to form a gap. The display device includes a backplate and is arranged on the backplate. The middle frame includes a support part and a fixing part connected to the support part, the support part is arranged on the two panels and covers the gap. The fixing part is arranged in the gap and is detachably connected to the backplate. The LED substrate is arranged on the support part.

Abstract: An electro-optical device is provided and includes a first light-emitting element configured to emit light in a first wavelength region, a second light-emitting element configured to emit light in a second wavelength region shorter than the first wavelength region, a third light-emitting element configured to emit light in a third wavelength region shorter than the second wavelength region, a first filter configured to transmit light in the first wavelength region and light in the second wavelength region and absorb light in the third wavelength region, and a second filter configured to transmit light in the first wavelength region and light in the third wavelength region and absorb light in the second wavelength region.

Abstract: A stack package includes a core die disposed over a package substrate, and a controller die disposed between the core die and the package substrate to control the core die. The core die includes banks each including memory cell arrays, an interbank region in which row decoders and column decoders are arranged, and a pad region in which first connection pads electrically connected to the row decoders and column decoders through first wirings are disposed. The controller die includes a through via region in which controller die through vias penetrating the controller die to be connected to the first connection pads are disposed, and a circuit region in which controlling circuitry electrically connected to the controller die through vias through second wirings is disposed.

Abstract: An integrated circuit (IC) structure includes a first transistor and a second transistor. The first transistor includes a first active region and a first gate disposed on the first active region, in which the first gate has a first effective gate length along a first direction parallel to a lengthwise direction of the first active region. The second transistor includes a second active region and a second gate disposed on the second active region, and includes a plurality of gate structures arranged along the first direction and separated from each other, in which the second gate has a second effective gate length along the first direction, the second effective gate length is n times the first effective gate length, and n is a positive integer greater than 1.

Abstract: Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a substrate having a first area and a second area, a plurality of fin structures extending along a direction over the first area and the second area of the substrate, a first transistor and a second transistor in the first area, a first isolation structure disposed between the first transistor and the second transistor, a first isolation structure disposed between the first transistor and the second transistor, a third transistor and a fourth transistor in the second area, and a second isolation structure disposed between the third transistor and the fourth transistor. The first isolation structure includes a first width along the direction and the second isolation structure includes a second width along the direction. The second width is greater than the first width.

Abstract: A crystalline oxide thin film contains an In element, a Ga element and an Ln element, in which the In element is a main component, the Ln element is at least one element selected from the group consisting of La, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu, and an average crystal grain size D1 is in a range from 0.05 ?m to 0.5 ?m.

Abstract: A vertical non-volatile memory device capable of stably maintaining an operating temperature in a chip level, a semiconductor package including the memory device, and a heat dissipation method of the memory device. The vertical non-volatile memory device includes a substrate on which a cell array area and an extension area are defined, a vertical channel structure formed on the substrate, a thermoelectric device including at least two semiconductor pillars formed on the substrate, and a stacked structure on the substrate. The stacked structure includes a gate electrode layer and an interlayer insulation layer which are stacked alternately along sidewalls of the vertical channel structure and the at least two semiconductor pillars. The at least two semiconductor pillars include an n-type semiconductor pillar and a p-type semiconductor pillar which are electrically connected to each other through a conductive layer on the substrate.

Abstract: A method of producing a semiconductor memory device includes, when three directions crossing each other are set to first, second, and third directions, respectively, laminating a plurality of first laminates and a plurality of second laminates on a semiconductor substrate in the third direction. The method further includes forming ends of the plurality of first laminates in shapes of steps extending in the first direction, and forming ends of the plurality of second laminates in shapes of steps extending in both directions of the first direction and the second direction.

Abstract: According to one embodiment, a semiconductor memory device includes first to second areas, a plurality of conductive layers, first to fourth members, and a plurality of pillars. The second area includes a first contact area including first to third sub-areas. The conductive layers include first to fourth conductive layers. The first conductive layer includes a first terrace portion in the first sub-area. The second conductive layer includes a second terrace portion in the third sub-area. The third conductive layer includes a third terrace portion in the first sub-area. The fourth conductive layer includes a fourth terrace portion in the third sub-area.

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple to conductor material of the conductor tier. The insulative tier immediately-above a lowest of the conductive tiers comprises a lower first insulating material and an upper second insulating material above the upper first insulating material. The upper second insulating material is of different composition from that of the lower first insulating material. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. Other embodiments, including method, are disclosed.

Abstract: An embodiment provides a semiconductor device package and a light emitting device comprising same, the semiconductor device package comprising: a body including a first cavity; and a semiconductor device disposed within the first cavity, wherein: the first cavity includes a first surface inclined such that the area of the cavity gradually increases as going away from the semiconductor device, and a plurality of second surfaces perpendicular to the upper surface of the semiconductor device; the body includes a first outer surface and a third outer surface that are opposite to each other, a second outer surface and a fourth surface that are opposite to each other, a first corner portion disposed in a region where the first and second outer surfaces meet each other, a second corner portion disposed in a region where the second and third outer surfaces meet each other, a third corner portion disposed in a region where the third and fourth outer surfaces meet each other, and a fourth corner portion disposed in a r

Abstract: Described examples include sensor apparatus and integrated circuits having a package structure with an internal cavity and an opening that connects of the cavity with an ambient condition of an exterior of the package structure, and an electronic sensor structure mechanically supported by wires in the cavity and including a sensing surface exposed to the cavity to sense the ambient condition of an exterior of the package structure.

Abstract: The present disclosure provides a semiconductor structure, including a first semiconductor device having a first surface and a second surface, the second surface being opposite to the first surface, a semiconductor substrate over the first surface of the first semiconductor device, and a III-V etch stop layer in contact with the second surface of the first semiconductor device. The present disclosure also provides a manufacturing method of a semiconductor structure, including providing a temporary substrate having a first surface, forming a III-V etch stop layer over the first surface, forming a first semiconductor device over the etch stop layer, and removing the temporary substrate by an etching operation and exposing a surface of the III-V etch stop layer.

Abstract: A method of forming an array of memory cells includes forming lines of covering material that are elevationally over and along lines of spaced sense line contacts. Longitudinal orientation of the lines of covering material is used in forming lines comprising programmable material and outer electrode material that are between and along the lines of covering material. The covering material is removed over the spaced sense line contacts and the spaced sense line contacts are exposed. Access lines are formed. Sense lines are formed that are electrically coupled to the spaced sense line contacts. The sense lines are angled relative to the lines of spaced sense line contacts and relative to the access lines. Other embodiments, including structure independent of method, are disclosed.

Abstract: A display device includes a plurality of sub-pixels. The sub-pixels include, in common, a common hole-transport layer disposed between an anode and a light-emitting layer. Each sub-pixel individually includes an individual hole-transport layer disposed between the common hole-transport layer and the light-emitting layer. The common hole-transport layer is made of a first hole-transport-layer material. A sub-pixel has a first color and includes a first individual hole-transport layer made of a second hole-transport-layer material. A sub-pixel has a second color and includes a second individual hole-transport layer made of a mixed material of the first and second hole-transport-layer materials.

Abstract: Methods for selective deposition, and structures thereof, are provided. Material is selectively deposited on a first surface of a substrate relative to a second surface of a different material composition. A passivation layer is selectively formed from vapor phase reactants on the first surface while leaving the second surface without the passivation layer. A layer of interest is selectively deposited from vapor phase reactants on the second surface relative to the passivation layer. The first surface can be metallic while the second surface is dielectric, or the second surface is dielectric while the second surface is metallic. Accordingly, material, such as a dielectric, can be selectively deposited on either metallic or dielectric surfaces relative to the other type of surface using techniques described herein. Techniques and resultant structures are also disclosed for control of positioning and shape of layer edges relative to boundaries between underlying disparate materials.