Patents Examined by Mary Anne Wilczewski
  • Patent number: 4945070
    Abstract: A CMOS device having shallow source and drain regions is formed in a body of single crystalline silicon having a major surface by forming in the body adjacent well regions of opposite conductivity type having an isolation region of an insulating material extending into the body from the major surface along the junction of the well regions. Thin layers of silicon oxide are formed on the major surface over each of the well regions, and a gate line of conductive polycrystalline silicon is formed over each of the silicon oxide layers. The side walls of the gate lines are covered with a layer of silicon oxide. A layer of polycrystalline silicon is selectively deposited on the surface of the body at each side of each gate line and on the gate lines. A layer of a refractory metal is deposited on the polycrystalline silicon layer. The polycrystalline silicon layer is heated to cause the metal to react with the silicon and form a metal silicide region at least partially through the polycrystalline silicon layer.
    Type: Grant
    Filed: January 24, 1989
    Date of Patent: July 31, 1990
    Assignee: Harris Corporation
    Inventor: Sheng T. Hsu
  • Patent number: 4888304
    Abstract: The present semiconductor device comprises a first semiconductor substrate, an oxide film formed on the substrate and a second semiconductor substrate bonded to the oxide film. In particular, the semiconductor substrate further has a monocrystalline silicon layer which is formed by an epitaxial growth method on the second semiconductor substrate. Circuit elements are formed within the monocrystalline silicon layer.
    Type: Grant
    Filed: December 22, 1986
    Date of Patent: December 19, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kaoru Nakagawa, Yoshio Yamamoto, Nobutaka Matsuoka
  • Patent number: 4797108
    Abstract: An a-Si FET comprising electrically conductive source and drain regions supported by an insulating substrate; a layer of amorphous silicon which is separately deposited in a space between said source and drain regions so as to engage the source and drain regions; source and drain electrodes electrically connected with said source and drain regions respectively; a gate electrode disposed adjacent said layer of amorphous silicon; and an insulating layer separating the gate electrode from the amorphous silicon layer; the arrangement being such that, in the ON state of the FET, a direct current-path is established in the layer of amorphous silicon which is disposed in said space. A low cost, low-temperature substrate such as soda glass may be used and the a-Si FET may be of the thin film type. Such an a-Si FET can be used in an LCD device which is addressed using one or more of the FET's.
    Type: Grant
    Filed: December 10, 1986
    Date of Patent: January 10, 1989
    Assignee: Lucas Industries Public Limited Company
    Inventor: Simon N. Crowther