Abstract: A mechanism is provided in a data processing system for asynchronous replication. The mechanism creates a record in a write log in a host computing device for a write command and marking the record as uncommitted. The mechanism maintains a copy of data to be written by the write command at the host computing device. The mechanism issues the write command from the host computing device to a primary storage controller at the primary storage site. Responsive to receiving an acknowledgement from the primary storage controller that the data have been written to the primary storage site, the mechanism marks the record as unreplicated. Responsive to receiving an acknowledgement from the primary storage controller that the data have been replicated to a secondary storage site, the mechanism erases the record in the write log and deleting the copy of data.

Abstract: Embodiments are disclosed relating to garbage collecting storage blocks in a storage device. In one embodiment, data is selected for relocation from a storage block in a storage device during reclaiming of the storage block. The data may be selected based on metadata that identifies whether data is valid at a time when the reclaiming is initiated. In some embodiments, prior to relocating data from the storage block, the metadata is captured from a data structure that identifies whether data on the storage device is valid. In one embodiment, a determination of whether the selected data has become invalid due to other data that is stored during the reclaiming is made. In some embodiments, in response to determining that the selected data has become invalid, the selected data is specified as invalid in the data structure.

Abstract: A processor in a multi-processor configuration is configured perform dynamic address translation from logical addresses to real address and to detect memory conflicts for shared logical memory in transactional memory based on logical (virtual) addresses comparisons.

Abstract: The memory power consumption is reduced more than in the past by performing a power control suitably for a nonvolatile memory. A memory control circuit is provided with a first register group for a CPU to perform separately initial setting of the operation mode (power OFF, standby, and power ON) of plural banks included in a nonvolatile memory, for every task of a program executed by the CPU, and an access determination unit which determines a bank to which an access from the CPU takes place, on the basis of the access address for instruction fetching and the kind of the fetched instruction. The memory control circuit switches the operation mode of each of the banks on the basis of the setting value of the first register group, and the determination result of the access determination unit.

Abstract: A method of operating a storage device that controls input/output of multi-stream data according to a stream ID may include receiving, from a host, a stream control command controlling at least a first stream ID and a second stream ID, determining, in response to the received stream control command, a third stream ID including control commands for the first and second stream IDs, and transmitting the third stream ID to the host.

Abstract: A higher level shared cache of a hierarchical cache of a multi-processor system utilizes transaction identifiers to manage memory conflicts in corresponding transactions. The higher level cache is shared with two or more processors. Transaction indicators are set in the higher level cache corresponding to the cache lines being accessed. The transaction aborts if a memory conflict with the transaction's cache lines from another transaction is detected.

Abstract: Methods and apparatus for providing region zero-fill on demand for tiered memory including a first region in a first memory tier having a page cache in physical memory, where virtual memory includes a mmap of the first region. An input can be controlled between zeroes and the first region to the page cache.

Abstract: Systems and methods are described to reserve cache space of points of presence (“POPs”) within a content delivery network (“CDN”). A provider may submit a request to the CDN to reserve cache space on one or more POPs for data objects designated by that provider. Thereafter, the CDN may mark those designated data objects within its cache as protected from eviction. When the CDN implements a cache eviction policy on the cache, the protected objects may be ignored for purposes of eviction, or may be evicted only after non-protected data objects.

Abstract: The disclosed technology includes techniques for efficiently streaming media content from a multi-tiered storage system. An example implementation may be used for adaptive HTTP streaming of video segments and other content. In some implementations, flash memory SSDs (SLC or MLC) may form an intermediate cache layer between a first layer of DRAM cache and third layer of HDDs. Significant architectural elements of various implementations include optimal write granularity to overcome the write amplification effect of flash memory SSDs and a QoS-sensitive caching strategy that monitors the activity of the flash memory SSDs to ensure that video streaming performance is not hampered by the caching activity.

Abstract: Determining, by a processor having a cache, if data in the cache is to be monitored for cache coherency conflicts in a transactional memory (TM) environment. A processor executes a TM transaction, that includes the following. Executing a memory data access instruction that accesses an operand at an operand memory address. Based on either a prefix instruction associated with the memory data access instruction, or an operand tag associated with the operand of the memory data access instruction, determining whether a cache entry having the operand is to be marked for monitoring for cache coherency conflicts while the processor is executing the transaction. Based on determining that the cache entry is to be marked for monitoring for cache coherency conflicts while the processor is executing the transaction, marking the cache entry for monitoring for conflicts.

Abstract: Methods and apparatus for obtaining property data for an object that is monitored for change, wherein the data source contains data for a current cycle. Further obtaining property data for the object for a previous cycle and comparing the property data for the object for the current and previous cycles to generate a change event when the property data for the object for the current and previous cycles do not match.

Abstract: A higher level shared cache of a hierarchical cache of a multi-processor system utilizes transaction identifiers to manage memory conflicts in corresponding transactions. The higher level cache is shared with two or more processors. A processor may have a corresponding accelerator that performs operations on behalf of the processor. Transaction indicators are set in the higher level cache corresponding to the cache lines being accessed. The transaction aborts if a memory conflict with the transaction's cache lines from another transaction is detected, and the corresponding cache lines are invalidated. For a successfully completing transaction, the corresponding cache lines are committed and the data from store operations is stored.

Abstract: Embodiments of the present invention provide a method, system, and computer program product for allocating storage extents. Extent input/output information pertaining to an extent on a storage device is received, by a computer, where the extant input/output information includes an access rate of data stored on the extent. The computer determines one or more periods of time where the input/output information exceeds a preconfigured threshold. The computer generates one or more of a first policy and a second policy based on the determined one or more periods where the first policy includes allocating the extent to a high performance disk within a tier storage system when data is stored during the determined periods and the second policy includes reallocating the extent from a low performance disk within the tier storage system to a high performance storage device within the tier storage system during the one or more determined periods.

Abstract: Physical memory of a storage processor is organized into a general section and a cache section, where the general section is available as machine memory for instructions and data of an operating system, and the cache section is unavailable as machine memory to the operating system and used by privileged components for caching storage data in connection with processing of storage I/O requests. A cache manager operates with a virtualizing component to allocate and organize units of the cache section into guest physical memory for a guest virtual machine executing on the storage processor. Upon the guest virtual machine accessing memory in a guest virtual memory address space, corresponding physical memory accesses of the guest physical memory are performed. The virtualizing component is a virtual machine monitor such as the kernel virtual machine (KVM) extension of Linux®.

Abstract: A system and method for providing consistent performance in a storage device, such as a solid state drive. A threshold value for command execution time for a command in a category of command (e.g., a read command or a write command) and a command size, is stored in the storage device. When a host command in the category (e.g., a read command) and corresponding size is received, the storage device executes the command, and if it completes execution of the command in a time that is less than the threshold value, the solid state drive waits until an amount of time equal to the threshold value has elapsed before sending the command completion.

Abstract: Storage systems track free blocks using various data structures and maps. For instance, free block maps may contain data blocks with values that indicate whether a block is free or not. When an operation results in a block being freed, the relevant data block in the maps must be written during an I/O operation to update the value. Large numbers of updates my occur after an operation that frees a large numbers of blocks, which can lead to performance degradation. Accordingly, disclosed are systems and methods for deferring updating of free block data tracking structures using logs.

Abstract: A computer allows non-cacheable loads or stores in a hardware transactional memory environment. Transactional loads or stores, by a processor, are monitored in a cache for TX conflicts. The processor accepts a request to execute a transactional execution (TX) transaction. Based on processor execution of a cacheable load or store instruction for loading or storing first memory data of the transaction, the computer can perform a cache miss operation on the cache. Based on processor execution of a non-cacheable load instruction for loading second memory data of the transaction, the computer can not-perform the cache miss operation on the cache based on a cache line associated with the second memory data being not-cached, and load an address of the second memory data into a non-cache-monitor. The TX transaction can be aborted based on the non-cache monitor detecting a memory conflict from another processor.

Abstract: An information processing apparatus comprises a plurality of processor elements, and a memory having a plurality of banks. Statistical information representing an access frequency distribution to each memory area of the memory by the plurality of processor elements is obtained. An allocation process of allocating the banks to the memory areas is performed based on the statistical information.

Abstract: Determining, by a processor having a cache, if data in the cache is to be monitored for cache coherency conflicts in a transactional memory (TM) environment. A processor executes a TM transaction, that includes the following. Executing a memory data access instruction that accesses an operand at an operand memory address. Based on either a prefix instruction associated with the memory data access instruction, or an operand tag associated with the operand of the memory data access instruction, determining whether a cache entry having the operand is to be marked for monitoring for cache coherency conflicts while the processor is executing the transaction. Based on determining that the cache entry is to be marked for monitoring for cache coherency conflicts while the processor is executing the transaction, marking the cache entry for monitoring for conflicts.

Abstract: Systems and methods for generating random address mapping in non-volatile memories using local and global interleaving are provided. One such method for generating a random address mapping for a non-volatile memory (NVM) involves identifying a number of bits (N) in a physical address space of the NVM, selecting G bit(s) of the N bits to be used for global interleaving, where G is less than N, determining a number of bits (N?G) to be used for local interleaving, mapping the G bit(s) using a mapping function for global interleaving, interleaving (N?G) bits using an interleaving function for local interleaving, and generating a combined mapping comprising the mapped G bit(s) and the interleaved (N?G) bits.