Abstract: A laser-annealing method includes the steps of a first step of cleaning a non-monocrystal silicon film formed on a substrate, and a second step of laser-annealing the non-monocrystal silicon film in an atmosphere containing oxygen therein, wherein the first and second steps are conducted continuously without being exposed to the air. Also, a laser-annealing device includes a cleaning chamber, and a laser irradiation chamber, wherein a substrate to be processed is transported between the cleaning chamber and the laser irradiation chamber without being exposed to the air.

Abstract: A method of treating an electrically non-conductive tunnel barrier layer through an overlayer of a tunnel junction device with ultra-violet light is disclosed. The method includes irradiating a tunnel barrier layer with ultra-violet light through at least one overlayer that covers the tunnel barrier layer to activate oxygen or nitrogen atoms disposed in the barrier layer so that those atoms will react with a target material of the tunnel barrier layer to form a uniformly oxidized or nitridized tunnel barrier layer having minimal or no defects therein and/or a desired breakdown voltage. The ultra violet light can irradiate the tunnel barrier layer during or after the formation of the overlayer. Heat can be applied before, during, or after the irradiation step to increase the activation rate and to further reduce defects. The method is applicable to any tunnel junction device including a magnetic field sensitive memory device such as a MRAM.

Abstract: An LCD panel is provided, the LCD panel having a substrate, a conductive layer positioned on the substrate, and a dielectric layer disposed on the surface of the conductive layer. First, a photoresist layer with an opening is formed on the dielectric layer. An etching process is then performed to form a contact hole along the opening. After that, a post treatment process is performed to form a protective layer to reduce damage on the conductive layer when the photoresist layer is stripped.

Abstract: A method of affixing a heat sink to a substrate and package thereof having a substrate with a position for receiving a semiconductor chip, at least a semiconductor chip for affixing on the position and electrically connecting the substrate, an appropriate thickness of adhesive agent by scraping by means of screen printing technology, a heat sink for covering the semiconductor chip and provided with a plurality of dimples for affixing to the substrate, the method including steps of affixing the semiconductor to the substrate and utilizing a scraper to apply a layer of adhesive agent with an appropriate thickness of adhesive on a platform from the adhesive agent; utilizing a sucker to move the heat sink to a position above the layer of adhesive agent, and dipping the dimples of the heat sink into the adhesive layer so as to adhere some adhesive agent onto the dimples, and then moving the heat sink above the semiconductor chip; affixing the heat sink to the substrate to cover the semiconductor chip; and enclosin

Abstract: A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device on a first surface of a silicon carbide substrate and with at least one metal contact for the device on the first surface of the substrate. The opposite, second surface of the substrate is then ground and polished until it is substantially transparent. The method then includes masking the polished second surface of the silicon carbide substrate to define a predetermined location for a via that is opposite the device metal contact on the first surface; etching the desired via through the desired masked location until the etch reaches the metal contact on the first surface; and metallizing the via to provide an electrical contact from the second surface of the substrate to the metal contact and to the device on the first surface of the substrate.

Abstract: A computerized method and system for automatically extracting an IEEE 1149.1 standard design from a netlist and performing compliance checking. The present invention receives the TAP (test access port) description and compliance enable ports of a netlist. The TAP controller is extracted and its state ports are identified, referenced in a boundary scan design database (BSDD) and its states are verified. The TAP controller is controlled so that the instruction register is located and referenced in the BSDD. The TAP controller is controlled so that the bypass register is found and the BSDD is updated. The TAP controller is controlled so that the shift and update cells of the boundary scan register (BSR) are found, the control, input and output BSR cells are characterized and the BSDD is updated. Primary input and output information is also inferred and the device_ID register is found. Frontier pins are used to locate signatures of the remaining instructions and their test data registers are found.

Abstract: The present invention is directed to providing a generalized system and method for enabling circuit design and fabrication in the delta sigma domain. In accordance with exemplary embodiments, a framework for such a system is based on a library of generalized operators that can receive multiple inputs, and that can be randomly chained together. Further, the operators are specifically configured to guarantee valid (e.g., bounded and/or stable) results, and to provide closure within the delta sigma domain; that is, to produce valid intermediate results in the delta sigma domain. Linear operators are configured to provide closure by complying with at least two criteria: (1) with respect to linear operators, at least one of (a) the inputs and (b) the output of a portion of the operator used to implement a mathematical function is scaled (e.g., normalized) to guarantee valid results; and (2) outputs from each mathematical operation are remodulated into a single bit stream in the delta sigma domain.

Abstract: After a cobalt film 12 and a titanium nitride film 13 as a barrier film against oxygen are formed over the surfaces of impurity diffusion layers 9, 10 on a silicon substrate 1, a first heat treatment is performed at a temperature below 400° C., forming a Co2Si film 31. Following this, the titanium nitride film and the unreacted cobalt film are removed, using a mixed solution of sulfuric acid and hydrogen peroxide and then another heat treatment is performed at a temperature in a range of 700˜900° C. and thereby forms a CoSi2 film. According to the present invention, the generation of spikes of cobalt silicide which may pierce the diffusion layers is well suppressed and, thus, the leakage current is well-controlled so that good transistor characteristics as well as high reliability are attained.

Abstract: The polyurethane-resin layer and adhesive layer marking strip composition is conformant to the roadway without tearing, has a high elongation, a high permanent deformation, and a low elastic return due to high molecular weight and high sterical impediment.One example of a high molecular weight and high sterical impediment is a sterically-impeded high-volume aromatic ring which reduces crystallization.