Abstract: A linked list memory (8) having an address generator (19) used during initial processing and a method for assigning addresses to lists corresponding to devices using a common memory (10). When the address generator (19) has assigned each address location once, a free list is used to track available addresses. The free list is not used until all addresses have been assigned once. In one embodiment, a counter (22) is incremented each time an address is assigned, where the value of counter (22) provides the address for a write operation. The counter (22) is not effected by requests to read from memory. The free list is not used until the counter (22) has been used to assign all addresses in the memory (10).

Abstract: A method and apparatus for allowing developers to develop software for their product. The method includes providing a first mode signal to a processor to operate in a development mode. The method also includes executing instructions stored in a first region of the memory in response to the first mode signal, providing data to the processor, and writing the data into a second region of the memory.

Abstract: In a computer system including a processor, a system memory, a flash memory, and a memory controller, memory address/window detector coupled to the processor, the memory controller, a first input of a OR logic gate and a first input of an AND gate. The OR logic gate has an output coupled to the memory controller and a second input for receiving a system memory access enable signal. Also included is a memory window control coupled to the system memory, the memory controller, the flash memory, the memory address/window detector, an output of a NOT logic gate and a first input of another AND logic gate. The additional AND logic gate has a second input for receiving a flash memory programming enable signal. A system memory access enable register is included and is coupled to an output of the first AND logic gate, a second input of the OR logic gate, and an input of the NOT logic gate. The memory window control is only accessible when the system memory access enable register is set to disabled.

Abstract: A cache coherency protocol uses a “Tagged” coherency state to track responsibility for writing a modified value back to system memory, allowing intervention of the value without immediately writing it back to system memory, thus increasing memory bandwidth. The Tagged state can migrate across the caches (horizontally) when assigned to a cache line that has most recently loaded the modified value. Historical states relating to the Tagged state may further be used. The invention may also be applied to a multi-processor computer system having clustered processing units, such that the Tagged state can be applied to one of the cache lines in each group of caches that support separate processing unit clusters. Priorities are assigned to different cache states, including the Tagged state, for responding to a request to access a corresponding memory block. Any tagged intervention response can be forwarded only to selected caches that could be affected by the intervention response, using cross-bars.

Abstract: A method for caching information objects is provided. Information objects are stored in portions of a non-volatile storage device called arenas, which are contiguous regions from which space is allocated in parallel. Objects are contiguously allocated within an arena and are mapped to directory tables that provide an efficient search mechanism. Each object is identified by a name key and a content key. The name key is constructed by applying a hash function to the composition of the name or URL of the object along with implicit or explicit context about the request. The content key is constructed by applying a hash function to the entire contents of the object data. Buckets and blocks in the directory tables store tags and subkeys derived from the keys. Since duplicate objects that have different names will hash to the same content key, the cache can detect duplicate objects even though they have different names, and store only one copy of the object.

Abstract: A system adaptively adjusts the phases of a plurality of internal clock signals, each respective internal clock signal causing a corresponding latch to store a digital signal responsive to the respective internal clock signal. The system includes a plurality of clock control circuits, each clock control circuit controlling the phase of a respective internal clock signal relative to a corresponding external clock signal responsive to a respective phase command signal. A plurality of evaluation circuits are coupled to the respective latches, each comparing the plurality of digital signals stored in the corresponding latch to expected values and generating a result signal indicating the results of this comparison. A phase selector circuit operates in a storage mode to sequentially develop a plurality of phase command signals on an output and store a corresponding result signal sequentially received on an input.

Abstract: A microcontroller is presented including additional hardware which generates additional address signals needed to expand the memory address space of the microcontroller. The additional address signals allow access to memory locations within external memory devices which would not otherwise be accessible while advantageously maintaining software compatibility with previous microcontroller products. The most significant address signals divide memory locations within the external memory devices into multiple memory banks of equal size. The remaining least significant address signals are used to access memory locations within each memory bank. When memory banking is enabled, software instructions select the desired memory bank by writing appropriate values to address bit positions within one or more memory banking registers. In a first embodiment, additional “auxiliary” address signals have values stored within corresponding bit positions of a memory banking control (MBC) register.

Abstract: A hybrid cache/SIRO buffer system includes a latch array for storing data words corresponding to system addresses; read command generator circuitry for launching data read commands to a memory system; a write pointer; write circuitry for storing data arriving from the memory system into the latch array at the location indicated by the write pointer; lowest and highest pointers for indicating the locations in the latch array corresponding to a lowest and a highest system address for which a read command has been launched; read circuitry for retrieving data from the latch array randomly; and control circuitry. Responsive to a first read request by a host system, the system begins retrieving data from memory beginning with an address equal to or close to the address associated with the first read request; then it speculatively reads ahead. As read requests from the host system continue to be processed by the system, more speculative reads are executed until the buffer is nearly full of data.

Abstract: A method for improved memory management during the processing of binary decision diagrams in a computer system. Prior to creating a new node in memory, a find operation is performed to determine if that node already exists in memory. A hash key is computed for the new node and a hash table is accessed to retrieve a pointer to a linked list of nodes which are potential matches for the new node. The linked list is in increasing order of the chronological age of the nodes. The nodes are sequentially retrieved from main memory in the order of the linked list. The retrieval is terminated at the last linked node which was created subsequent to the child nodes of the new node.

Abstract: To produce monocrystalline layers of conducting or semiconducting materials on porous monocrystalline layers of the same material in a reproducible and time-saving manner, a method is provided which involves applying an amorphous layer of the same material to the porous material and converting the amorphous layer to a monocrystalline layer by tempering.

Abstract: An apparatus comprises an Si-disposing section in which solid Si is disposed; a seed-crystal-disposing section in which a seed crystal of SiC is disposed; a synthesis vessel adapted to accommodate the Si-disposing section, the seed-crystal-disposing section, and carbon; heating means adapted to heat the Si-disposing section and the seed-crystal-disposing section; and a control section for transmitting to the heating means a command for heating the Si to an evaporation temperature of Si or higher and heating the seed crystal to a temperature higher than that of Si; wherein the Si evaporated by the heating means is adapted to reach the seed-crystal-disposing section.

Abstract: A method of planarizing a copper containing conductive layer of a semiconductor wafer forms a blanketing copper containing layer within and upon a patterned substrate layer. Chemical mechanical polish (CMP) planarizing is performed on the copper containing layer at a relatively fast rate of removal until most of the layer is removed. The remaining portion of the layer is then CMP planarized at a second rate of removal, which is slower than the first rate of removal, until the copper containing layer is substantially completely removed and a barrier layer underlying the copper containing layer is reached. The multiple phase planarization of the copper containing layer avoids excessive dishing and pattern erosion while maintaining high throughput and uniform removal.

Abstract: A reaction assembly of a vapor-phase deposition system includes a reaction chamber leading to a gullet outlet, and a sheath leading to a sheath outlet. The gullet outlet and the sheath outlet at the distal end of the reaction assembly, the distal end including a compound nozzle. The reaction assembly generates a compound gas stream for projection from the compound nozzle towards a target substrate. The compound gas stream includes a reagent gas stream and a sheath gas stream, wherein the sheath gas stream at least partially envelopes the reagent gas stream. Methods for generating and delivering a compound gas stream, and for performing vapor-phase deposition, are also disclosed.

Abstract: A method of minimizing repetitive chemical-mechanical polishing scratch marks from occurring on a polished semiconductor wafer surface resulting from breaking away of surface peaks having an elevation of at least 400 nanometers above an outer surface immediately adjacent said peaks comprises improving adherence of said peaks to the wafer by filling at least a portion of the volume between adjacent peaks with a material and chemical-mechanical polishing the peaks and the material at the same time. A method of minimizing undesired node-to-node shorts of a length less than or equal to 0.3 micron formed laterally along an insulating dielectric layer in a monolithic integrated circuit chip comprises depositing a sacrificial layer of material over the dielectric layer and chemical-mechanical polishing completely through the sacrificial layer and into the dielectric layer prior to depositing any metal over the insulating dielectric layer.

Abstract: There is disclosed a method of producing a silicon monocrystal using a Czochralski method in which a sharp tip end of a seed crystal is brought into contact with silicon melt and is melted, and the seed crystal is then pulled, without performance of a necking operation, in order to grow a silicon monocrystalline ingot below the seed crystal. The operation of melting the seed crystal into the silicon melt is performed in a state in which a temperature in the vicinity of the surface of the silicon melt is set in a range between a temperature 25.degree. C. higher than the melting point of silicon and a temperature 45.degree. C. higher than the melting point of silicon. The operation of growing the monocrystal is started within 0 to 10 minutes after completion of the operation of melting the sharp tip end of the seed crystal into the silicon melt. The monocrystal is grown at a rate in a range of 0.3 to 0.7 mm/min when growth of the monocrystal is started after completion of the melting operation.

Abstract: A method of growing a nitride semiconductor crystal which has very few crystal defects and can be used as a substrate is disclosed. This invention includes the step of forming a first selective growth mask on a support member including a dissimilar substrate having a major surface and made of a material different from a nitride semiconductor, the first selective growth mask having a plurality of first windows for selectively exposing the upper surface of the support member, and the step of growing nitride semiconductor portions from the upper surface, of the support member, which is exposed from the windows, by using a gaseous Group 3 element source and a gaseous nitrogen source, until the nitride semiconductor portions grown in the adjacent windows combine with each other on the upper surface of the selective growth mask.

Abstract: A method for effectively removing copper residue from surfaces of a semiconductor wafer includes the step of immersing the semiconductor wafer having the copper residue into an acidic solution and then into a basic cleaning solution. The acidic solution includes hydrogen fluoride (HF) and hydrogen chloride (HCl) for breaking bonds within the copper residue which may include for example dicopper oxide (Cu.sub.2 O), copper oxide (CuO), and organic copper residue such as copper benzotriazole (Cu-BTA complex). The basic cleaning solution includes tetramethylammonium hydroxide ((CH.sub.3).sub.4 NOH) and surfactant (RE-610) for effectively acting as an emulsifier to rinse away the copper residue having broken bonds from the semiconductor wafer. The present invention may be practiced to particular advantage when the semiconductor wafer is immersed in deionized water after immersion in the acidic solution and after immersion in the basic cleaning solution.

Abstract: A polishing process to planarize a layer formed on a substrate and to reduce the variations in the thickness of that layer from substrate to substrate. The polishing process is implemented by polishing a substrate using a stable pad material. A stable pad material is formed from a polishing material that has substantially the same or similar density, hardness, and compressibility as polyurethane but is a material other than or substantially other than polyurethane. In an alternative embodiment, the material for the polishing pad may be selected for its compression, high tensile strength, wear resistance and/or resistance to water, diluted acids, and alkalis. In a further alternative embodiment, the material forming the polishing pad may be selected from the group comprising hydrogenated nitrile compounds, fluoroelastomers, or perfluoroelastomers.

Abstract: The invention relates to a p-type silicon macromolecule, with a multifaceted structure in which silicon atoms form the corners of an inner multifaceted structure having sides. Attached to each silicon atom is a doping atom. The doping atoms are attached to the silicon atoms and radiate out from the center of the molecule to form an outer multi-faceted structure having sides parallel to the inner multifaceted structure. The macromolecule forms a base facility in a transistor that comprises an emitter layer, a collector layer, connected to the base facility, and a control input structure. The control input structure comprises a dipole connected to a boundary surface on the transistor and at least one external modulation capacitor connected to the dipole. The capacitor receives a carrier signal from a control input signal. The dipole is spaced from the center a boundary surface by half a wavelength of the carrier signal.

Abstract: A method of introducing nitrogen into a melt for use in producing a nitrogen-doped silicon single crystal by the Czochralski method includes adding a silicon material to a vessel, such as a quartz crucible, adding a nitrogen-containing powder, preferably silicon nitride powder, to the vessel, and heating the vessel for a time sufficient to melt the silicon material and to dissolve the nitrogen-containing in the silicon material in order to form the melt. A nitrogen-doped silicon single crystal is then produced from the melt by the Czochralski method by pulling the silicon single crystal from the melt with a seed crystal.