Abstract: Apparatus and method of assisting software emulation of hardware functions in a processor. During a read cycle on an address bus, an address that is within a predetermined address range is stored in a trap register and a Type-of-Cycle bit in the trap register is set to the read state. If an Issue-SMI-on-Next-Access bit in the trap register is set to the on state, a system management interrupt is issued to the processor. During a write cycle, data on the data bus is stored in a data field of the trap register, the address is stored in the address field of the trap register and the Type-of-Cycle bit is set to the write state. A system management interrupt is issued if the Issue-SMI-on-Next-Access bit is set to the on state. Then the Issue-SMI-on-Next-Access bit is set to the off state. The Type-of-Cycle bit of the trap register is set if the system management interrupt is detected at the processor.

Abstract: A method for creating a shell to represent a functional block of an IC design comprising of a plurality of interconnected functional blocks. The critical information from a synthesized gate level block is retained in the shell such that when analyzing the static characteristics of another block connected to the block now represented by the shell the analysis is still accurate. At a hierarchial level the present invention provides a method for analyzing the functional blocks of an IC design such that the memory requirement for storing the information of the functional blocks of the IC design is reduced as well as a decrease in run time.

Abstract: A testing system for, and method of, simulating signal flow through a logic block pattern of a real time process control system. The system includes: (1) a memory that contains a data base of input data associated with simulated sensors and a rule base containing control rules and constituting a logic block pattern and (2) a processor that operates in an arbitrary time base to apply the input data to the control rules to simulate signal flow through the logic block pattern and thereby produce simulated output data and real time control system responses thereby testing the logic block pattern, the memory and the processor being detached from the real time process control system to prevent use of resources thereof in connection with the logic block pattern testing.

Abstract: A method and data processing system for emulating a program are disclosed. According to the present invention, the data processing system runs under a first operating system and emulates the execution of a program under a second operating system within a second data processing system. The data processing system includes a memory which stores at least a portion of the first operating system and an emulator comprising a plurality of routines which each emulate an instruction utilized by the first operating system. The memory further includes a simulated mass storage data area which stores at least a portion of the program and a simulated main memory data area. The data processing system further includes a processor which executes instructions within the program under the first operating system by emulation. According to the present invention, the emulator accesses instructions of the program directly from the simulated mass storage data area to minimize emulation overhead.

Abstract: A domino logic simulator for a CMOS domino logic circuit seeds all logic circuits under test with an "X" state before initialization of a special simulator machine cycle devoted to validating all pre-charge circuits in each stage of the CMOS domino logic circuit. In the special machine cycle, each stage of the circuit receives a discrete clock signal which is applied to the pre-charge and logic devices in precharge and evaluation phase sequences. The clock phase sequences in each stage propagate the "X" state at each logic circuit through the succeeding stages to provide an "X" output for the machine cycle, except a "0" state is provided as an output at the end of the machine cycle if the precharge circuit in each stage is functioning properly during the precharge sequences of the clock cycle applied to the stage. A clocked delay reset circuit in each stage provides the output of the stage. A static logic device in each stage saves power in transferring the output of a stage to a succeeding stage.

Abstract: Low power linear digital signal processing circuits are fabricated based on a design synthesis process using activity metrics. The average activity value .theta..sub.i of all the input nodes of the circuit is determined. Architectural transformations of the circuit are performed in order to minimize the average activity value over all the nodes. The transformation resulting in the minimum activity value is the synthesized design used as the basis for fabricating a low power linear digital signal processing circuit.

Abstract: A method used by an electronic design automation system for stabilizing the names of components and nets of an integrated circuit from one design version to another. A previous integrated circuit design version and a current integrated circuit design version are partitioned into multiple cones of logic design. Each cone of logic design is defined by a path from a logic designer-defined apex net to a logic designer-defined base net affecting the apex net. Selected cones of logic design are compared. If the selected cones have identical logical structure, the component and net names of the previous integrated circuit design version are transferred to the current integrated circuit design version.

Abstract: An apparatus (10) for selecting a vehicle seat and obtaining user information includes a CPU (11) connected to an input device (12), a monitor (13), a speaker (14) and a memory (15). A method of operating the apparatus (10) includes storing a plurality of vehicle interior photographs in the memory (15), generating screens on the monitor (13) and audio on the speaker (14) requesting user related information be entered utilizing the input device (12), utilizing the user entered information to select a vehicle having the seat best suited for the user, displaying the stored photograph of the selected vehicle interior on the monitor (13) and storing the user entered information in the memory (15).

Abstract: The present invention is directed to an apparatus for and a method of automatically creating a supplemental segment in two-dimensional drawings. Two-dimensional drawing data concerning at least three views depicted based on orthogonal projection is previously stored in a drawing data storage device. Knowledge for recognizing three-dimensional solid model restored on the basis of the two-dimensional drawing data is previously stored in a knowledge storage device. The knowledge stored in the knowledge storage device is applied to the two-dimensional drawing data stored in the drawing data storage device, so that the three-dimensional solid model restored on the basis of the two-dimensional drawing data is recognized. An area where the supplemental segment is to be created is determined in the two-dimensional drawings on the basis of the recognized three-dimensional solid model. At least two end points of the supplemental segment to be created are determined in the determined area.

Abstract: A system and method for verifying the correct behavior of instruction and data fetches and the order of instruction and data fetch resource modifications by a speculative and or out-of-order computer architecture under test is presented. An architectural model which models the high-level architectural requirements of the computer architecture under test, including instruction fetch resources and data fetch resources, executes test stimuli instructions in natural program order. A behavioral model, which models the high-level architectural requirements of the computer architecture, including instruction fetch resources and data fetch resources, executes the same test stimuli instructions, but according to the speculative and or out-of-order instruction execution behavior defined by the computer architecture under test.

Abstract: A method and system for automatically generating panel layout and wiring harness specifications for vehicles. The panel layout system receives as input a list of parts including switches, gauges, connectors, circuit breakers, etc., and automatically places these parts in a control panel (e.g. dash panel or electrical panel) within the vehicle. To place these parts automatically, the system extracts potential panel locations for each part from a database, and then attempts to place the parts in their corresponding potential panel locations. The system can also generate a wiring specification for the vehicle. Once panel locations are assigned, the system attempts to assign circuits in the wiring harness to electrical contact locations associated with panel locations.

Abstract: A process simulation apparatus simulates a manufacturing process of a semiconductor device which manufacturing process comprising various processes including an ion implantation process and a diffusion process. Process sequence data which represents conditions of a two-dimensional simulation for each process is input to a memory unit. The memory unit stores the process sequence data and also stores condition information for various simulation models usable for each process. An optimum simulation model for each process is selected for performing a two-dimensional simulation for each process. The semiconductor device manufacturing process is simulated by a two-dimensional simulation method using the selected optimum simulation model.

Abstract: In a Field Programmable Gate Array ("FPGA") design system, a configuration is generated. A path of the configuration is selected as a critical path for optimization. The critical path is optimized by rerouting connections between the logical primitives of the critical path. Prior to the rerouting, the logical primitives of the critical path may be optimally placed within the FPGA configuration. Optimal performance of the critical path is thus achieved.