Abstract: The present invention relates to a pop count-based deep learning neural network computation method, a multiply accumulator, and a device thereof. The computation method according to an exemplary embodiment of the present invention is a computation method for a deep learning neural network, including a step of generating one-hot encoding codes according to the type of first multiplication result values for a multiplication (first multiplication) of weights (W) and input values (A); a step of performing a pop-count for each generated code; and a step of accumulating result values for a constant multiplication (second multiplication) between each type of the first multiplication result value and each count value of the pop-count which are different constant values.

Abstract: An interleaved cascaded integrator-comb (“CIC”) filter receives an interleaved sensor output signal, including a plurality of digitized sensor signals at an input clock rate. An integrator of the interleaved CIC filter processes the interleaved signal to output an integrated interleaved signal. A downsampler of the interleaved CIC filter buffers portions of the integrated interleaved corresponding to a decimation rate for the interleaved signal. The portions of the signals are provided to a comb filter, which outputs a decimated interleaved signal.

Abstract: A multiplication-and-accumulation (MAC) circuit includes a MAC operator and a data input circuit. The MAC operator selectively performs a MAC arithmetic operation of weight data and vector data or an element-wise multiplication (EWM) arithmetic operation of the weight data and constant data. The data input circuit provides the MAC operator with the weight data and the vector data when the MAC operator performs the MAC arithmetic operation and provides the MAC operator with the weight data and the constant data when the MAC operator performs the EWM arithmetic operation.

Abstract: An integrated circuit for generating a product of an input and a constant includes a lookup table memory configured to store seeds corresponding to multiples of the constant, processing circuitry configured to generate a plurality of addresses respectively corresponding to a plurality of parts extracted from the input, configured to receive a plurality of seeds from the lookup table memory based on the plurality of addresses, and configured to generate a plurality of partial products based on the plurality of seeds. The processing circuitry is configured to sum the plurality of partial products. A number of the plurality of seeds stored in the lookup table memory is less than a number of possible values of the plurality of partial products.

Abstract: A neural network device includes a calculation circuit that includes a first multiplier, a second multiplier, an align shifter, and an adder. The adder shares the first multiplier and the second multiplier. The calculation circuit performs a first dot product operation on a plurality of floating point data pairs or a second dot product operation on a plurality of integer data pairs. In the first dot product operation, the calculation circuit obtains a plurality of fraction multiplication results from the plurality of floating point data pairs, respectively, using the first multiplier, adds the plurality of fraction multiplication results using the adder and outputs first cumulative data. In the second dot product operation, the calculation circuit obtains a plurality of integer multiplication results from the plurality of integer data pairs, respectively, using the second multiplier, adds the plurality of integer multiplication results using the adder, and outputs second cumulative data.

Abstract: A processing-in-memory (PIM) device includes a first memory region, a second memory region, a third memory region, and a multiplication-and-accumulation MAC circuit. The first memory region is configured to store weight data comprised of elements of a weight matrix. The second memory region is configured to store vector data comprised of elements of a vector matrix. The third memory region is configured to store constant data. The MAC circuit is configured to selectively perform a MAC arithmetic operation of the weight data and the vector data or an element-wise multiplication (EWM) arithmetic operation of the weight data and the constant data.

Abstract: In some examples, a device includes a first processing core comprising a resistive memory array to perform an analog computation, and a digital processing core comprising a digital memory programmable with different values to perform different computations responsive to respective different conditions. The device further includes a controller to selectively apply input data to the first processing core and the digital processing core.

Abstract: Apparatus includes hardware logic arranged to normalise an n-bit input number. The hardware logic comprises at least a first hardware logic stage, an intermediate hardware logic stage and a final hardware logic stage. Each stage comprises a left shifting logic element, the first and intermediate stages each also comprise a plurality of OR-reduction logic elements and the intermediate and final stages each also comprise one or more multiplexers. The OR-reduction logic elements operate on different subsets of bits from the number input to the particular stage. In the intermediate and final hardware logic stages, a first of the multiplexers selects an OR-reduction result received from a previous hardware logic stage and the left shifting logic element is arranged to perform left shifting on the updated binary number received from an immediately previous hardware logic stage dependent upon the selected OR-reduction result.

Abstract: The subject matter described herein provides systems and techniques for the design and use of multiply-and-accumulate (MAC) units to perform matrix multiplication by systolic arrays, such as those used in accelerators for deep neural networks (DNNs). These MAC units may take advantage of the particular way in which matrix multiplication is performed within a systolic array. For example, when a matrix A is multiplied with a matrix B, the scalar value, a, of the matrix A is reused many times, the scalar value, b, of the matrix B may be streamed into the systolic array and forwarded to a series of MAC units in the systolic array, and only the final values and not the intermediate values of the dot products, computed for the matrix multiplication, may be correct. MAC unit hardware that is particularized to take advantage of these observations is described herein.

Abstract: A representative reconfigurable processing circuit and a reconfigurable arithmetic circuit are disclosed, each of which may include input reordering queues; a multiplier shifter and combiner network coupled to the input reordering queues; an accumulator circuit; and a control logic circuit, along with a processor and various interconnection networks. A representative reconfigurable arithmetic circuit has a plurality of operating modes, such as floating point and integer arithmetic modes, logical manipulation modes, Boolean logic, shift, rotate, conditional operations, and format conversion, and is configurable for a wide variety of multiplication modes. Dedicated routing connecting multiplier adder trees allows multiple reconfigurable arithmetic circuits to be reconfigurably combined, in pair or quad configurations, for larger adders, complex multiplies and general sum of products use, for example.

Abstract: A systolic array can implement an architecture tailored to perform matrix multiplications on sparse matrices. Each processing element in the systolic array may include a register configured to store a value, and a multiplexor configured to select an input element from multiple input data buses based on metadata associated with the value. Each processing element may also include a multiplier configured to multiply the selected input element with the value to generate a multiplication result, and an adder configured to add the multiplication result to a partial sum input to generate a partial sum output.

Abstract: A circuit for transposing a matrix comprising reversal circuitry configured, for each of one or more diagonals of the matrix, to receive elements of the matrix in a first vector and generate a second vector that includes the elements of the matrix in an order that is a reverse of an order of the elements of the matrix in the first vector, and rotation circuitry configured, for each of the one or more diagonals of the matrix, to determine a number of positions by which to rotate the elements of the matrix in the second vector, receive the second vector of elements of the matrix, and generate a third vector that includes the elements of the matrix in the second vector in an order that is a rotation of the elements of the matrix in the second vector by the determined number of positions.

Abstract: A method and apparatus are provided for manufacturing integrated circuits performing invariant integer division x/d. A desired rounding mode is provided and an integer triple (a,b,k) for this rounding mode is derived. Furthermore, a set of conditions for the rounding mode is derived. An RTL representation is then derived using the integer triple. From this a hardware layout can be derived and an integrated circuit manufactured with the derived hardware layout. When the integer triple is derived a minimum value of k for the desired rounding mode and set of conditions is also derived.

Abstract: A multiplier circuit includes a first circuit comprising a first transistor, a second transistor, a first capacitor, and a second capacitor. It further includes a second circuit comprising a third transistor, a fourth transistor, a third capacitor, and a fourth capacitor.

Abstract: According to one embodiment, in a processing circuit of a computation system, a plurality of comparators corresponds to the respective columns, each including a first input node, a second input node, and an output node, the first input node receiving any one of the second signals, the second input node receiving a signal corresponding to a global reference signal provided to each second input node, the output node outputting a local signal. A global circuit is provided common to the plurality of comparators, the global circuit generating a global signal according to a plurality of the local signals, the global circuit generating the global reference signal by an SAR method according to the global signal. The processing circuit disables some of the plurality of comparators according to the local signals and the global signal.

Abstract: Examples described herein relate to instructions to request performance of tanh and sigmoid instructions. For example, a compiler can generate native tanh instructions to perform tanh. In some examples, a tanh function can be compiled into instructions that include an instruction to perform either tanh(input) or tanh(input)/input depending on a value of the input to generate an intermediate output; an instruction to cause a performance of generation of scale factor based on the input; and an instruction to cause performance of a multiplication operation on the intermediate result with the scale factor. For example, a sigmoid function can be compiled to cause a math pipeline to perform a range check and performs operations based on a range.

Abstract: Methods for evaluating quantum computing circuits in view of the resource costs of a quantum algorithm are described. A processor-implemented method for performing an evaluation of a polynomial corresponding to an input is provided. The method includes determining a polynomial interpolation for a set of sub-intervals corresponding to the input. The method further includes constructing a quantum circuit for performing, in parallel, polynomial evaluation corresponding to each of the set of sub-intervals.

Abstract: A digital signal processor (DSP), which may be implemented as a DSP block in a field programmable gate array (FPGA), includes a fracturable multiplier, a fracturable adder and a fracturable variable shifter. Further included is at least one sign-extension block, to provide for normal mode, dual-fracturing mode and quad-fracturing mode.

Abstract: Embodiments of the present disclosure propose a deep learning processing apparatus and method, device and storage medium, relating to the field of artificial intelligence.

Abstract: Techniques and mechanisms providing a mode of random number generation to satisfy a requirement for a consumer of random numbers. In an embodiment, a device comprises a Gaussian random number generator (GRNG) circuit, multiple uniform random number generator URNG circuits, and circuitry which is coupled between the GRNG circuit and the URNG circuits. Based on an indication of one or more required performance characteristics and/or one or more required statistical characteristics, a controller identifies a corresponding one of multiple available random number generation (RNG) modes. The controller communicates control signals to provide the mode with the circuitry. In another embodiment, the control signals configure the circuitry to select one or more of the URNG circuits for use in calculating random numbers with the GRNG circuit.