Abstract: Disclosed in the present invention are a dynamic maximal clique enumeration device and method based on an FPGA with an HBM, the method including: the HBM stores a dynamic edge flow, a complete graph adjacency matrix, and candidate cliques; a matrix computing unit updates the complete graph adjacency matrix based on the dynamic edge flow, transmits the updated complete graph adjacency matrix to the HBM for storage, and determines header nodes, of which the corresponding candidate clique needs to be updated; a sequence computing unit constructs, according to the updated complete graph adjacency matrix and each header node to be updated, the sorted data set for reconstructing candidate cliques by data block sequencing; and an update computing unit executes, in parallel, an update task of the candidate clique corresponding to each header node to be updated based on the sorted data set, transmits the updated candidate cliques to the HBM for storage, and transmits the updated candidate cliques to the PC host to ext

Abstract: Disclosed are devices, systems, and methods for performing time-domain multiply-and-accumulate (MAC) computations. In some embodiments, an apparatus comprises first and second circuits. The first circuit is configured to (a) perform a first multiplication in response to a trigger signal, the first multiplication being a product of a first value and a second value, and (b) generate a completion signal, wherein the completion signal indicates completion of the first multiplication. The second circuit is coupled to the first circuit and is configured to (i) perform a second multiplication in response to the completion signal, the second multiplication being a product of a third value and a fourth value, and (ii) generate an output signal, wherein the output signal indicates completion of the second multiplication. An amount of elapsed time between the trigger signal and the generation of the output signal represents a sum of the first and second multiplications.

Abstract: A matrix decomposition structure of a two-channel quadrature mirror filter bank, including an analysis filter part, a synthesis filter part, the filter part includes an E0,M module, an X module, a Y module, a Z module, an input port and an output port. The X module takes a value of the input port as an input of a multiplier, and the E0,M module delays the input. An output of the Xmodule passes through the Y module and then is used as an input of the Z module, and outputs of the Z module and the E0,M module are added and then output from the output port, and pass through a middle part to enter the synthesis filter part.

Abstract: A neural network device for performing a neural network operation includes a floating point arithmetic circuit configured to perform a dot-product operation for each of a plurality of floating point data pairs, wherein the floating point arithmetic circuit is configured to, in the dot-product operation, align-shift a plurality of fraction part multiplying operation results respectively corresponding to the floating point data pairs based on a maximum value determined from a plurality of exponent part adding operation results respectively corresponding to the floating point data pairs.

Abstract: A true random number generator (TRNG) is disclosed that includes an enclosure. The enclosure enfolds a radioactive source, defining a radioactive source surface and a cavity separating the radioactive source from an array of cells, which defines an array surface with an edge. Each cell in the array comprises a detector constructed to detect electrons within the cavity from the decay of the radioactive source and to produce a signal for the detected energy. A projection of the radioactive source surface onto the array surface extends beyond the edge and encompasses the array surface.

Abstract: Processing cores with data associative adaptive rounding and associated methods are disclosed herein. One disclosed processing core comprises an arithmetic logic unit cluster configured to generate a value for a unit of directed graph data using input directed graph data, a comparator coupled to a threshold register and a data register, a core controller configured to load a threshold value into the threshold register when the value for the unit of directed graph data is loaded into the data register, and a rounding circuit. The rounding circuit is configured to receive the value for the unit of directed graph data from the arithmetic logic unit cluster and conditionally round the value for the unit of directed graph data based on a comparator output from the comparator.

Abstract: A compute-memory circuit included in a computer system may include multiple compute data storage cells coupled to a compute bit line via respective capacitors. The compute data storage cells may store respective bits of a weight value. During a multiply operation, an operand may be used to generate a voltage level on a compute word line that is used to store respective amounts of charge on the capacitors, which are coupled to the compute bit line. The voltage on the compute bit line may be converted into multiple bits whose value is indicative of a product of the operand and the weight value.

Abstract: The present invention implements high-speed right shift computation and division in secure computation. According to the present invention, a public value multiplication part calculates [a?]=[2ua] from a distributed value [a] of a value “a.” A first conversion part converts [a?] into additive secret sharing. A right shift computation part calculates <s>i=<a?>i>>b+u. A second conversion part converts <s> into linear secret sharing. A first bit conversion part converts lower u bits of <a?>i into {a?i mod 2u}. A quotient transfer part 16 obtains lower u bits of ??i<m{a?i mod 2u} as {q}. A second bit conversion part converts lower b+u bits of <a?>i into {a?iR}={a?i mod 2b+u}. An addition part calculates {z}=?i<m{a?iR}+{q}, and obtains a bit sequence {zQ} of a (b+u)-th bit and after of {z}. A third conversion part converts {q} and {zQ} into linear secret sharing. An output computation part outputs [s]?[2l?(b+u)q]+[zQ] as [a>>b].

Abstract: The present invention provides a calculator capable of outputting results based on handwritten formulas, wherein the calculator has at least one writing area, and can output the calculation results of the handwritten formulas in the writing area, wherein the setting of the writing area does not compromise the functional completeness of the calculator compared to a traditional calculator, and also does not change the operating habits when using the calculator as a traditional calculator, that is, the calculator provides different methods to obtain calculation results and allows verification of the calculation results obtained using an alternative method. This reduces the probability of errors in the calculation results caused by user mistakes when compared to verifying the calculation results using the same method.

Abstract: A processing device comprises multiplier circuitry configured to output a product of mantissas represented by first and second signals in response to a mode signal and output a product of an integer represented by the first signal and a mantissa represented by the second signal in response to the mode signal. The processing device further includes an aligning circuit configured to shift a mantissa part of a third signal based on an exponent part of the third signal and an exponent of a product of the first and second signal to generate and output a shifted signal. The processing device further includes an arithmetic logic circuit configured to output a mantissa of a sum of a product of the first and second signals and the third signal in response to an output signal of the aligning circuit and an output signal of the multiplier circuitry.

Abstract: A signal processing circuit outputs, in a case where a first timing at which a first input signal changes is earlier than or same as a second timing at which a second input signal changes, a first output signal at the first timing and a second output signal at the second timing, and outputs, in a case where the first timing is later than the second timing, the first output signal and the second output signal at the second timing.

Abstract: A method for assigning a random number to a user in a set of users includes computing a random number assignment seed value based on an ASCII-value representation of the user's name, dividing the random number assignment seed value by a quantity of unassigned numbers available to be assigned to the user to produce a modified random number assignment seed value, rounding the modified random number assignment seed value down to an integer, computing a random number offset value by multiplying the quantity of unassigned numbers by the rounded modified random number assignment seed value, subtracting the random number assignment offset value from the random number assignment seed value to determine a random number assignment lookup number, determining the random number to be assigned to the user based on the random number assignment lookup number, and assigning the determined random number to the user.

Abstract: Described herein is a graphics processor including a processing resource including a multiplier configured to multiply input associated with the instruction at one of a first plurality of bit widths, an adder configured to add a product output from the multiplier with an accumulator value at one of a second plurality of bit widths, and circuitry to select a first bit width of the first plurality of bit widths for the multiplier and a second bit width of the second plurality of bit widths for the adder.

Abstract: A function generation apparatus includes a function setter, a data string selector, and a matrix generator. The function setter sets a target function in an apparatus to be controlled. The data string selector selects, from among data strings indicating a plurality of combinations of parameters that can be reflected in control in the apparatus to be controlled, data strings according to the function set by the function setter. The matrix generator generates a transformation matrix according to the target function using the data strings selected by the data string selector as elements.

Abstract: Disclosed herein is a low-cost, high-performance, and energy-efficient near-sensor convolution engine based on pulsed unary processing. The disclosed engine removes the necessity of using costly analog-to-digital converters. Synthesis results show that the proposed pulse-based design significantly improves the hardware cost and energy consumption compared to the conventional fixed-point binary and also to the stochastic computing-based designs.

Abstract: A computation unit 11 performs, for each column of a target matrix to be standardized, a computation process to compute the average and standard deviation of the value of each component of the column. A first dividing unit 12 performs, for each column of the target matrix, a first dividing process to divide the value of each component of the column by the standard deviation computed based on the column. A second dividing unit 13 performs, for each column of the target matrix, a second dividing process to divide the average computed based on the column by the standard deviation computed based on the column. A generation unit 14 which arranges the quotients computed by a plurality of second dividing processes, in a row in the order of the columns of the target matrix from which the quotients are computed, thereby generating a row vector.

Abstract: A computer-implemented method includes receiving performing a fused modular multiply and add operation to compute d=((a*b)+c) % p, wherein a, b, and c, are provided as a set of operands. A first multiply-and-accumulate unit computes a binary multiplication to compute a*b. A second multiply-and-accumulate unit computes a first intermediate result by updating a result of the binary multiplication using p. An accumulator of a third multiply-and-accumulate unit is initialized with c. The third multiply-and-accumulate unit computes a second intermediate result using the first intermediate result and c. An adder unit subtracts a portion of the second intermediate result from a portion of the result of the binary multiplication. The output of the adder is provided as a result of the fused modular multiply and add operation.

Abstract: A processing device may include multiplier circuitry configured to output a product of an integer represented by the first signal and a mantissa represented by the second signal. The processing device may further include a dynamic shifting circuit configured to shift a first shifted signal generated by shifting a mantissa part of a third signal based on the integer part of the first signal to generate and output a second shifted signal, and shift an output signal of the multiplier circuitry based on the integer part of the first signal to generate and output a third shifted signal. The processing device may further include an arithmetic logic circuit configured to output an signal representing a mantissa of a sum of a product of the first and second signals and the third signal based on output signals of the dynamic shifting circuit.

Abstract: A computer-implemented method comprising: obtaining an equation with a cost function for minimization related to an optimization problem thereby yielding a cost function equation, the cost function including two or more binary variables, converting the cost function equation into a Boolean formula in Conjunctive Normal; obtaining a Max-Clique problem by processing the Boolean formula; providing the Max-Clique problem to a Gaussian Boson Sampling, GBS, quantum device; and processing light output data of the GBS quantum device so as to find values of the two or more binary variables of the cost function.

Abstract: The present invention relates to a pop count-based deep learning neural network computation method, a multiply accumulator, and a device thereof. The computation method according to an exemplary embodiment of the present invention is a computation method for a deep learning neural network, including a step of generating one-hot encoding codes according to the type of first multiplication result values for a multiplication (first multiplication) of weights (W) and input values (A); a step of performing a pop-count for each generated code; and a step of accumulating result values for a constant multiplication (second multiplication) between each type of the first multiplication result value and each count value of the pop-count which are different constant values.