Patents Examined by Matthew D Sandifer

Patent number: 12001508Abstract: A plurality of chiplets may be used to multiply two matrices A and B. Matrix A may be decomposed into horizontal stripes and matrix B may be decomposed into vertical stripes. Each of the horizontal stripes may be multiplied by each of the vertical stripes to form the output matrix C. Specifically, horizontal stripes may be stored in a stationary, distributed manner across the chiplets, while the vertical stripes (or subvertical stripes) may be passed between respective pairs of the chiplets until each of the vertical stripes (or subvertical stripes) of matrix B has been received and processed by each of the chiplets. The vertical stripes may be passed along one or more paths that interconnect the chiplets. Similar techniques can be applied to an arrangement in which the vertical stripes are stationary and the horizontal stripes (or subhorizontal stripes) are passed between respective pairs of the chiplets.Type: GrantFiled: October 23, 2023Date of Patent: June 4, 2024Assignee: Persimmons, Inc.Inventor: James Michael Bodwin

Patent number: 11971949Abstract: A graphics processing unit (GPU) and a method is disclosed that performs a convolution operation recast as a matrix multiplication operation. The GPU includes a register file, a processor and a state machine. The register file stores data of an input feature map and data of a filter weight kernel. The processor performs a convolution operation on data of the input feature map and data of the filter weight kernel as a matrix multiplication operation. The state machine facilitates performance of the convolution operation by unrolling the data of the input feature map and the data of the filter weight kernel in the register file. The state machine includes control registers that determine movement of data through the register file to perform the matrix multiplication operation on the data in the register file in an unrolled manner.Type: GrantFiled: February 10, 2021Date of Patent: April 30, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Christopher P. Frascati, Simon Waters, Rama S. B Harihara, David C. Tannenbaum

Patent number: 11973519Abstract: Examples described herein relate to an apparatus comprising a central processing unit (CPU) and an encoding accelerator coupled to the CPU, the encoding accelerator comprising an entropy encoder to determine normalized probability of occurrence of a symbol in a set of characters using a normalized probability approximation circuitry, wherein the normalized probability approximation circuitry is to output the normalized probability of occurrence of a symbol in a set of characters for lossless compression. In some examples, the normalized probability approximation circuitry includes a shifter, adder, subtractor, or a comparator. In some examples, the normalized probability approximation circuitry is to determine normalized probability by performance of nonpower of 2 division without computation by a Floating Point Unit (FPU). In some examples, the normalized probability approximation circuitry is to round the normalized probability to a decimal.Type: GrantFiled: June 23, 2020Date of Patent: April 30, 2024Assignee: Intel CorporationInventors: Bhushan G. Parikh, Stephen T. Palermo

Patent number: 11962333Abstract: A datacompression analyzer can rapidly make a binary decision to compress or not compress an input data block or can use a slower neural network to predict the block's compression ratio with a regression model. A Concentration Value (CV) that is the sum of the squares of the frequencies and a Number of Zero (NZ) symbols are calculated from an unsorted symbol frequency table. A rapid decision to compress is signaled when their product CV*NZ exceeds a horizontal threshold THH. During training, CV*NZ is plotted as a function of compression ratio C % for many training data blocks. Different test values of THH are applied to the plot to determine true and false positive rates that are plotted as a Receiver Operating Characteristic (ROC) curve. The point on the ROC curve having the largest Youden index is selected as the optimum THH for use in future binary decisions.Type: GrantFiled: August 19, 2022Date of Patent: April 16, 2024Assignee: Hong Kong Applied Science and Technology Research Institute Company LimitedInventors: Hailiang Li, Yan Huo, Tao Li

Patent number: 11943353Abstract: A computer processing system having an isogenybased cryptosystem for randomizing computational hierarchy to protect against sidechannel analysis in isogenybased cryptosystems.Type: GrantFiled: December 17, 2020Date of Patent: March 26, 2024Assignee: PQSecure Technologies, LLCInventors: Brian C. Koziel, Rami El Khatib

Patent number: 11934799Abstract: Combinatorial logic circuits with feedback, which include at least two combinatorial logic elements, are disclosed. At least one of the combinatorial logic elements receives an external input (i.e., from outside the circuit), at least one of the combinatorial logic elements receives an input that is feedback of the circuit output, and at least one of the combinatorial logic elements receives an input that is neither an external input nor an output of the circuit but rather is from another of the combinatorial logic elements and thus only “implicit” to the circuit. No staticizers are needed; the logic circuits effectively create implicit equations to perform functions that were previously thought to require sequential logic. The combinatorial logic circuits result in a stable output (in some instances after a brief period of time) due to the implicit equations, rather than achieving stability from an explicit expression of some input to the circuit.Type: GrantFiled: August 12, 2021Date of Patent: March 19, 2024Assignee: SiliconIntervention Inc.Inventor: A. Martin Mallinson

Patent number: 11934797Abstract: A processor to facilitate execution of a singleprecision floating point operation on an operand is disclosed. The processor includes one or more execution units, each having a plurality of floating point units to execute one or more instructions to perform the singleprecision floating point operation on the operand, including performing a floating point operation on an exponent component of the operand; and performing a floating point operation on a mantissa component of the operand, comprising dividing the mantissa component into a first subcomponent and a second subcomponent, determining a result of the floating point operation for the first subcomponent and determining a result of the floating point operation for the second subcomponent, and returning a result of the floating point operation.Type: GrantFiled: April 4, 2019Date of Patent: March 19, 2024Assignee: Intel CorporationInventors: Abhishek Rhisheekesan, Shashank Lakshminarayana, Subramaniam Maiyuran

Patent number: 11928176Abstract: A system and method for multiplying matrices are provided. The system includes a processor coupled to a memory and a matrix multiply accelerator (MMA) coupled to the processor. The MMA is configured to multiply, based on a bitmap, a compressed first matrix and a second matrix to generate an output matrix including, for each element i,j of the output matrix, a calculation of a dot product of an ith row of the compressed first matrix and a jth column of the second matrix based on the bitmap. Or, the MMA is configured to multiply, based on the bitmap, the second matrix and the compressed first matrix and to generate the output matrix including, for each element i,j of the output matrix, a calculation of a dot product of an ith row of the second matrix and a jth column of the compressed first matrix based on the bitmap.Type: GrantFiled: November 24, 2020Date of Patent: March 12, 2024Assignee: Arm LimitedInventors: ZhiGang Liu, Paul Nicholas Whatmough, Matthew Mattina

Patent number: 11914974Abstract: According to some embodiments, a system comprises a generator of a truly random signal is connected to an input and feedback device for the purpose of providing a user with real time feedback on the random signal. The user observes a representation of the signal in the process of an external physical event for the purpose of finding a correlation between the random output and what happens during the physical event. In some examples, the system is preferably designed such the system is shielded from all classically known forces such as gravity, physical pressure, motion, electromagnetic fields, humidity, etc. and/or, such classical forces are factored out of the process as much as possible. The system is thus designed to be selectively response to signals from living creatures, in particular, humans.Type: GrantFiled: November 30, 2020Date of Patent: February 27, 2024Assignee: Psyleron, Inc.Inventors: John Valentino, Herb Mertz, Ian Cook

Patent number: 11909421Abstract: A MAC operator includes a plurality of data type converters and a plurality of multipliers. Each of the plurality of data type converters may receive 16bit input data of one of first to fourth data types of a floatingpoint format to convert into Lbit output data of the floatingpoint format. Each of the plurality of multipliers may perform a multiplication on the “L”bit output data of the floatingpoint format outputted from two of the plurality of data type converters to output multiplication result data of the floatingpoint format.Type: GrantFiled: March 1, 2021Date of Patent: February 20, 2024Assignee: SK hynix Inc.Inventor: Choung Ki Song

Patent number: 11907330Abstract: Methods, systems, and apparatus for a matrix multiply unit implemented as a systolic array of cells are disclosed. Each cell of the matrix multiply includes: a weight matrix register configured to receive a weight input from either a transposed or a nontransposed weight shift register; a transposed weight shift register configured to receive a weight input from a horizontal direction to be stored in the weight matrix register; a nontransposed weight shift register configured to receive a weight input from a vertical direction to be stored in the weight matrix register; and a multiply unit that is coupled to the weight matrix register and configured to multiply the weight input of the weight matrix register with a vector data input in order to obtain a multiplication result.Type: GrantFiled: February 17, 2023Date of Patent: February 20, 2024Assignee: Google LLCInventors: Andrew Everett Phelps, Norman Paul Jouppi

Patent number: 11907680Abstract: A multiplicationaccumulation (MAC) includes a multiplication circuit, a preprocessing circuit, and an adder tree. The multiplication circuit performs a multiplication operation on a plurality of weight data and a plurality of vector data each having a floatingpoint format to output a plurality of multiplication data. The preprocessing circuit performs shifting on mantissa data of the plurality of multiplication data by a difference between first maximum exponent data having a greatest value among the exponent data of the plurality of multiplication data and the remaining exponent data to output a plurality of preprocessed mantissa data. The adder tree adds the plurality of mantissa data to output mantissa addition bits.Type: GrantFiled: April 19, 2022Date of Patent: February 20, 2024Assignee: SK hynix Inc.Inventor: Choung Ki Song

Patent number: 11899741Abstract: A memory device includes a memory configured to store input data and filter data for a convolution operation, and a function processor configured to, in response to a read command of at least a portion of data from among the input data and the filter data, transform the at least a portion of the data based on a parameter of the convolution operation during a clock cycle corresponding to the read command and output a corresponding transformation result as transformed data.Type: GrantFiled: April 23, 2020Date of Patent: February 13, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: HyungDal Kwon, Seung Wook Lee

Patent number: 11899745Abstract: Disclosed herein includes a system, a method, and a device for processing and converting data using matrix operations. Circuitry can partition an input of a first data format across a plurality of lookup tables each residing in a respective memory. The circuitry can access weight information from a load store memory, and the partitioned input on a per column basis from the plurality of lookup tables. The circuitry can perform a number of multiplyaccumulate (MAC) operations per cycle between the weight information from the load store memory and the partitioned input read on a per column basis from the plurality of lookup tables. The number of MAC operations performed per cycle can correspond to a total number of columns of the plurality of lookup tables. The circuitry can generate, responsive to the MAC operations on the partitioned input, a plurality of outputs in a second data format.Type: GrantFiled: August 19, 2020Date of Patent: February 13, 2024Assignee: Meta Platforms Technologies, LLCInventors: Alagappan Valliappan, Ganesh Venkatesh, Pierce IJen Chuang

Patent number: 11893078Abstract: A dot product multiplier for matrix operations for an A matrix of order 1×m with a coefficient B matrix of order m×m. Processing Elements (PEs) are arranged in an m×m array, the columns of the array summed to provide a dot product result. Each of the PEs contains a sign determiner and a plurality of analog multiplier cells, one multiplier cell for each value bit. The multipliers operate over four clock cycles, initializing a capacitor charge according to sign on a first clock phase, sharing charge on a second phase, canceling charge on a third phase, and outputting the resultant charge on a fourth phase, the resultant charge on each column representing the dot product for that column.Type: GrantFiled: August 29, 2020Date of Patent: February 6, 2024Assignee: Ceremorphic, Inc.Inventors: Aravinth Kumar Ayyappannair Radhadevi, Sesha Sairam Regulagadda

Patent number: 11894821Abstract: A Scalable Finite Impulse Response (“SFIR”) filter includes a preprocessing section, a postprocessing section, and a finite impulse response (“FIR”) Matrix. The FIR Matrix is coupled to the preprocessing section and the postprocessing section. The FIR Matrix includes a plurality of filter taps and a plurality of signal paths. Each filter tap of the plurality of filter taps has at least a first input, a second input, a multiplexer coupled to the first input and the second input, and a first flipflop coupled to an output of the multiplexer. The plurality of signal paths are arranged to allow reconfigurable data throughput between the each filter tap of the plurality of filter taps.Type: GrantFiled: February 12, 2020Date of Patent: February 6, 2024Assignee: The Boeing CompanyInventors: Kristine M. Skinner, Tyler J. Thrane, Jason A. Ching

Patent number: 11893360Abstract: A process for performing vector dot products receives a row vector and a column vector as floating point numbers in a format of sign plus exponent bits plus mantissa bits. The process generates a single dot product value by separately processing the sign bits, exponent bits, and mantissa bits to form a sign bit, a normalized mantissa formed by multiplying pairs multiplicand elements, and exponent information including MAX_EXP and EXP_DIFF. A second pipeline stage receives the multiplied pairs of normalized mantissas, optionally performs an exponent adjustment, pads, complements and shifts the normalized mantissas, and the results are added in a series of stages until a single addition result remains, which is normalized using MAX_EXP to form the floating point output result.Type: GrantFiled: February 21, 2021Date of Patent: February 6, 2024Assignee: Ceremorphic, Inc.Inventor: Dylan Finch

Patent number: 11886832Abstract: An operation device includes a quantizer circuit, a buffer circuit, a convolution core circuit and a multiplyadd circuit. The quantizer circuit receives first feature data and performs asymmetric uniform quantization on the first feature data to obtain and store in the buffer circuit second feature data. The quantizer circuit further receives a first weighting coefficient and performs symmetric uniform quantization on the first weighting coefficient to obtain and store in the buffer circuit a second weight coefficient. The convolution core circuit performs a convolution operation on the initial operation result, an actual quantization scale factor and an actual bias value to obtain a final operation result.Type: GrantFiled: December 28, 2020Date of Patent: January 30, 2024Assignee: SIGMASTAR TECHNOLOGY LTD.Inventors: Xiaofeng Li, Chengwei Zheng, Bo Lin

Patent number: 11886505Abstract: A function approximation system is disclosed for determining output floating point values of functions calculated using floating point numbers. Complex functions have different shapes in different subsets of their input domain, making them difficult to predict for different values of the input variable. The function approximation system comprises an execution unit configured to determine corresponding values of a given function given a floating point input to the function; a plurality of look up tables for each function type; a correction table of values which determines if corrections to the output value are required; and a table selector for finding an appropriate table for a given function.Type: GrantFiled: April 5, 2022Date of Patent: January 30, 2024Assignee: GRAPHCORE LIMITEDInventors: Jonathan Mangnall, Stephen Felix

Patent number: 11886377Abstract: A representative reconfigurable processing circuit and a reconfigurable arithmetic circuit are disclosed, each of which may include input reordering queues; a multiplier shifter and combiner network coupled to the input reordering queues; an accumulator circuit; and a control logic circuit, along with a processor and various interconnection networks. A representative reconfigurable arithmetic circuit has a plurality of operating modes, such as floating point and integer arithmetic modes, logical manipulation modes, Boolean logic, shift, rotate, conditional operations, and format conversion, and is configurable for a wide variety of multiplication modes. Dedicated routing connecting multiplier adder trees allows multiple reconfigurable arithmetic circuits to be reconfigurably combined, in pair or quad configurations, for larger adders, complex multiplies and general sum of products use, for example.Type: GrantFiled: September 9, 2020Date of Patent: January 30, 2024Assignee: Cornami, Inc.Inventor: Raymond J. Andraka