Abstract: A modular operation circuit includes a controller, a modular multiplier and a modular adder. The controller divides a first number into K segments. The modular multiplier performs modular multiplication operations and the modular adder performs modular addition operations to the K segments in (K?1) iterations for deriving a remainder of a division of the first number by a second number.

Abstract: In-memory arithmetic processors for the “n-bit” by “n-bit” multiplication, the “n-bit” by “n-bit” addition, and the “n-bit” by “n-bit” subtraction operations are disclosed. The in-memory arithmetic processors of the invention can obtain the operational resultant integer in the binary format for two inputted integers represented by two “n-bit” binary codes in one-step processing with no sequential multiple-step operations as for the conventional arithmetic binary processors. The in-memory arithmetic processors are implemented by a 2-dimensional memory array with X and Y decoding for the two inputted operational integers in the arithmetic binary operations.

Abstract: A MAC operator includes a plurality of multipliers configured to perform a multiplication operation on a floating-point format first data and a floating-point format second data to output a floating-point format multiplication result data, a plurality of floating-point-to-fixed-point converters configured to receive the floating-point format multiplication result data from each of the plurality of multipliers and convert into a fixed-point format multiplication result data to be output, and an adder tree configured to perform an addition operation on the fixed-point format multiplication result data that is output from the plurality of floating-point-to-fixed-point converters. If a first mantissa of the first data and a second mantissa of the second data are composed of ‘M’-bit (‘M’ being a natural number), each of the plurality of multipliers is configured to perform the multiplication operation so that the fixed-point format multiplication result data includes a mantissa of 2*(M+1) bits.

Abstract: A processing element, a neural processing device including the same, and a method for calculating thereof are provided. The processing element includes a weight register configured to receive and store weights, an input activation register configured to store input activations, a flexible multiplier configured to receive the weight and the input activation, to perform a multiplication calculation in a first precision or a second precision different from the first precision according to a mode signal, occurrence of an overflow, and occurrence of an underflow, and to generates result data; and a saturating adder configured to receive the result data and generate subtotals.

Abstract: A tile of an FPGA includes a multiple mode arithmetic circuit. The multiple mode arithmetic circuit is configured by control signals to operate in an integer mode, a floating-point mode, or both. In some example embodiments, multiple integer modes (e.g., unsigned, two's complement, and sign-magnitude) are selectable, multiple floating-point modes (e.g., 16-bit mantissa and 8-bit sign, 8-bit mantissa and 6-bit sign, and 6-bit mantissa and 6-bit sign) are supported, or any suitable combination thereof. The tile may also fuse a memory circuit with the arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased.

Abstract: A system includes a memory and a node. The memory stores first and second log string correlithm objects. The node receives first and second real-world numerical values, and identifies a first sub-string correlithm object from the first log string correlithm object that corresponds to the first real-world numerical value. The node aligns the first and second log string correlithm objects such that the first sub-string correlithm object aligns with a sub-string correlithm object from the second log string correlithm object representing the logarithmic value of one. The node identifies a second sub-string correlithm object from the second log string correlithm object that corresponds to the second real-world numerical value, and determines which sub-string correlithm object from the first log string correlithm object aligns with the second sub-string correlithm object from the second log string correlithm object. The node outputs the determined sub-string correlithm object.

Abstract: Processing cores with data associative adaptive rounding and associated methods are disclosed herein. One disclosed processing core comprises an arithmetic logic unit cluster configured to generate a value for a unit of directed graph data using input directed graph data, a comparator coupled to a threshold register and a data register, a core controller configured to load a threshold value into the threshold register when the value for the unit of directed graph data is loaded into the data register, and a rounding circuit. The rounding circuit is configured to receive the value for the unit of directed graph data from the arithmetic logic unit cluster and conditionally round the value for the unit of directed graph data based on a comparator output from the comparator.

Abstract: A processing-in-memory (PIM) device includes a multiplication/accumulation (MAC) operator. The MAC operator includes a multiplying block and an adding block. The multiplying block includes a first multiplier and a second multiplier. The first multiplier performs a first multiplying calculation of first half data of first data and first half data of second data. The second multiplier performs a second multiplying calculation of second half data of the first data and second half data of the second data. The adding block performs an adding calculation of first multiplication result data outputted from the first multiplier and second multiplication result data outputted from the second multiplier. The MAC operator receives a test mode signal having a first level to perform a test operation for the multiplying block.

Abstract: A controller is a controller of an array including a neuromorphic element that multiplies a weight based on a value of a variable characteristic by a signal, and includes a control unit that controls the characteristic of the neuromorphic element by using a discretization step size obtained so that a predetermined condition for reducing an error or a predetermined condition for improving accuracy is satisfied on the basis of a case where a true value of the weight obtained with a higher accuracy than a resolution of the characteristic of the neuromorphic element is used and a case where a discretization step size which is set for the characteristic of the neuromorphic element is used.

Abstract: An information processing device includes: a processor configured to: calculate a combination of t and q minimizing a computation time when q computation cores compute convolution between first matrices and second matrices of t-row t-column with Winograd algorithm in parallel, where a total number of elements of the first and second matrices does not exceed a number of sets of data that can be stored in each of q storage areas of a register, and the q computation cores correspond to the q storage areas; and output a program for causing a computing machine including the q computation cores and the register to execute a process including: storing the first and second matrices in each of the q storage areas with a calculated combination of t and q, and computing convolution between the first matrix and the second matrix with the Winograd algorithm by each of the q computation cores.

Abstract: Median values for a stream of received data values in a data processing system (e.g. an image processing system) are determined. A first median value of the received data values within a first subset of data values of the received stream is determined, and intermediate data used for determining the first median value is stored. The stored intermediate data is used to determine a median value of the received data values within a second subset of data values of the received stream, wherein the second subset at least partially overlaps with the first subset. The determined median values are outputted for use in the data processing system, e.g. for further processing.

Abstract: Technologies for performing in-memory macro operations include a memory having a media access circuitry connected to a memory media. The media access circuitry is to receive a request to perform an in-memory macro operation indicative of a set of multiple in-memory operations. The media access circuitry is also to perform, in response to the request, the in-memory macro operation on data present in the memory media.

Abstract: A combined adder for N logical bits to produce a sum from a first addend having N first addend bits and a second addend having N second addend bits. A least significant adder produces a segment sum of the least significant bits and a carry out. Segment adder pairs are used for each higher order of significant sums. One segment adder produces a segment sum portion, and the other produces an incremented segment sum portion. Carry logic associated with each segment is utilized with a multiplexer to select the incremented segment sum portion or the segment sum portion. The selected segment sum portions are assembled with a most significant carry out to produce the sum.

Abstract: Methods, systems, and apparatus for a matrix multiply unit implemented as a systolic array of cells are disclosed. Each cell of the matrix multiply includes: a weight matrix register configured to receive a weight input from either a transposed or a non-transposed weight shift register; a transposed weight shift register configured to receive a weight input from a horizontal direction to be stored in the weight matrix register; a non-transposed weight shift register configured to receive a weight input from a vertical direction to be stored in the weight matrix register; and a multiply unit that is coupled to the weight matrix register and configured to multiply the weight input of the weight matrix register with a vector data input in order to obtain a multiplication result.

Abstract: An arithmetic processing apparatus includes: a plurality of nodes (N nodes) capable of communicating with each other, each of the plurality of nodes including a memory and a processor, the memory being configured to store a value and an operation result, the processor being configured to execute first processing when N is a natural number of 2 or more, n is a natural number of 1 or more, and N?2n, wherein the first processing is configured to divide by 2 a value held by a first node, the first node being any of the plurality of nodes and a last node in an order of counting, obtain one or more node pairs by pairing remaining nodes among the plurality of nodes exception for the first node, and calculate repeatedly an average value of values held by each node pair of the one or more node pairs.

Abstract: A MAC operator includes a plurality of multipliers, a plurality of floating-point to fixed-point converters, and an adder tree. Each of the plurality of multipliers may perform a multiplication operation on first data and second data of a floating-point format to output multiplication result data. Each of the plurality of floating-point to fixed-point converters may convert the data type of the multiplication result data into a fixed-point format. The adder tree may perform a first addition operation on the multiplication result data of the fixed-point format. Each of the plurality of floating-point to fixed-point converters may skip a ‘+1’ operation for processing a negative number and a ‘+1’ operation for roundup processing in a data type converting process, and output round bits equaling to bit values not added by the skipped ‘+1’ operations in the data type converting process.

Abstract: A MAC operator includes a plurality of multipliers, a plurality of floating-point to fixed-point converters, an adder tree, an accumulator, and a fixed-point to floating-point converter. Each of the plurality of multipliers may perform a multiplication operation on first data and second data of a single-precision floating-point (FP32) format to output multiplication result data of the FP 32 format. Each of the plurality of floating-point to fixed-point converters may convert the FP 32 format into a fixed-point format. The adder tree may perform a first addition operation on the data of the fixed-point format. The accumulator may perform an accumulation operation on the data output from the adder tree. And the fixed-point to floating-point converter may convert the data of the fixed-point format into data of the FP32 format.

Abstract: In a general aspect, an optimization problem is solved using a hybrid computing system. A classical processor unit receives a first data structure that represents the optimization problem. The classical processor unit executes a branch-and-bound process on the first data structure to generate values for a first subset of elements of a solution to the optimization problem. A second data structure is generated based on the first data structure and the first subset of elements. The second data structure represents a reduced version of the optimization problem. A quantum processor unit and a classical processor unit are used to execute a quantum approximate optimization algorithm (QAOA) on the second data structure to generate values for a second subset of the elements of the solution to the optimization problem. The first subset and second subset are combined to obtain the solution to the optimization problem.

Abstract: A calculation processor for determining a digital output value from a digital input value based on an exponent value a, the processor comprising a first calculation block, a second calculation block and a final calculation block. The first calculation block initializes an intermediate value and an error value depending on a position of a Most Significant Bit of a significant part of the input value. The second calculation block is configured to perform repeatedly, until an exit criterion is fulfilled, the incrementation of a counter value, the determination of a power error value based on the error value and, if the power error value is larger than or equal to an error threshold, adjustment of the intermediate value y by multiplying the intermediate value with an adaptation value and setting the error value to the power error value divided by the base value. If the power error value is smaller than the error threshold, the error value is set to the power error value.

Abstract: Detailed are embodiments related to bit matrix multiplication in a processor. For example, in some embodiments a processor comprising: decode circuitry to decode an instruction have fields for an opcode, an identifier of a first source bit matrix, an identifier of a second source bit matrix, an identifier of a destination bit matrix, and an immediate; and execution circuitry to execute the decoded instruction to perform a multiplication of a matrix of S-bit elements of the identified first source bit matrix with S-bit elements of the identified second source bit matrix, wherein the multiplication and accumulation operations are selected by the operation selector and store a result of the matrix multiplication into the identified destination bit matrix, wherein S indicates a plural bit size is described.