Patents Examined by Matthew David
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Patent number: 9940223Abstract: The human-machine interface test system enables the automated testing of vehicle interface systems and consumer electronics devices, replacing testing and validation that previously had required human interaction. The human-machine interface device (HMI test object or device under test) does not need to be altered (via hardware or software modifications or additions) to be able to be tested using the human-machine interface test system. The HMIts involves the automated audio input generation and output analysis, visual verification of a display screen with graphics and texts display, including touch and gesture interface control and feedback, external device interface, as well as data logging for communication between the HMI device and the rest of the system, that will replace the testing and validation that previously required human interaction.Type: GrantFiled: April 7, 2014Date of Patent: April 10, 2018Assignee: FEV North America Inc.Inventors: Stephan A. Tarnutzer, Edward J. Frank, Brian A. Fischer, Guy N. Kennerly, William Osipoff, Joseph W. Priskorn
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Patent number: 8984319Abstract: A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device determines whether to initialize to a standard protocol or to an advanced protocol. Upon determining to initialize to the advanced protocol, the second remote device then waits for a synchronization point sequence.Type: GrantFiled: November 8, 2013Date of Patent: March 17, 2015Assignee: Texas Instruments IncorporatedInventor: Gary L. Swoboda
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Patent number: 8949499Abstract: The standard hot-plug controller (SHPC) specification may be used to generate PCI messages in a distributed switch to disconnect and/or connect virtual hierarchies of an endpoint from hosts that are connected based on multi-root input/output virtualization (MR-IOV). A management controller may instruct a SHPC to generate a PCI packet that specifies a particular virtual hierarchy to disconnect from a particular host. An upstream port connected to the host and the SHPC receives the PCI packet and uses a header that identifies the virtual endpoint in the packet to index into a routing table to identify a downstream port in the distributed switch that is connected to the endpoint. Once the PCI packet traverses the switch and arrives at the downstream port, the downstream port changes routing logic which logically disconnects the host from the specified virtual hierarchy.Type: GrantFiled: June 20, 2012Date of Patent: February 3, 2015Assignee: International Business Machines CorporationInventors: Ronald E. Freking, Elizabeth A. McGlone, Daniel R. Spach, Curtis C. Wollbrink
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Patent number: 8949500Abstract: Described embodiments provide a system having a bridge for connecting two different processor buses. The bridge receives a request from a first bus, the request having an identification field having a value. The request is then entered into one of a plurality of buffers having requests therein with the same identification field values. Which buffer receives the request may be based on a variety of techniques, such as random, least recently used, most full, prioritized, or sequential. Next, the buffered request is transmitted over a second bus. A response to the request is eventually received from the second bus, the response is transmitted over the first bus, and the request is then removed from the buffer. By entering the received request to the buffer with request with the same identification value, there is a reduced possibility of head-of-line request blocking when compared to a single buffer implementation.Type: GrantFiled: March 1, 2012Date of Patent: February 3, 2015Assignee: LSI CorporationInventors: Richard J. Byrne, David S. Masters
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Patent number: 8949652Abstract: In one embodiment, a microprocessor includes one or more processing cores. At least one processing core includes a clock shaping circuit that is configured to receive a clock input signal. The clock shaping circuit includes rising edge skew logic that is configured to selectively delay a rising edge of the clock input signal and falling edge skew logic that is configured to selectively delay a falling edge of the clock input signal independent of adjustment of the rising edge.Type: GrantFiled: November 3, 2011Date of Patent: February 3, 2015Assignee: Nvidia CorporationInventor: Chi Keung Lee
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Patent number: 8886982Abstract: A system for controlling power usage in a storage cluster by dynamically controlling membership in the storage cluster is disclosed. The storage cluster includes multiple storage servers that provide access to one or more storage subsystems. The power management system uses a power management policy to set parameters for controlling membership in the storage cluster and monitors the storage cluster based on the policy. Based on the monitoring, the system detects when the number of storage servers in the storage cluster should be reduced or increased. To reduce the number, the system selects a storage server to deactivate and directs the selected storage server to migrate storage resources (e.g., data, metadata) associated with the server to a different storage server. The system then deactivates the selected storage server by directing it to transition to a low power mode. The system may increase the number of servers in the storage cluster by reversing these steps.Type: GrantFiled: April 24, 2013Date of Patent: November 11, 2014Assignee: NetApp, Inc.Inventor: Dean Kalman