Abstract: A boundary scan controller and method. The boundary scan controller generates an output clock for shifting output data to a target device as a serial stream. The boundary scan controller generates another clock for receiving a serial stream of input data from the target device. The input clock is generated after the output clock according to a predetermined delay. The predetermined delay provides a period of time for the target device to respond to the serial stream of output data. The boundary scan controller comprises a clock generator for generating a system clock, a transmit module having a transmit clock generator and an output data register, a receive module having a receive clock generator and an input data register, and a state machine controller. The receive module includes a delay counter for generating a delay between the transmit and receive data clocks.

Abstract: A semiconductor integrated circuit device with fault analysis function performs test operation for a memory circuit (such as a RAM) in which a comparison control circuit (6) generates a comparison control signal CCMP in order to select one or more memory cells in each memory cell group (34, 35, 36 and 37) corresponding to a single bit, a specified row, a specified bit, or a specified pattern, and then outputs the comparison control signal CCMP to scan flip flops (2, 3, 4 and 5) each including a comparator (292). The comparator (292) performs the comparison operation between data and expected values EXP and then outputs a comparison result only when address signals are input and data are red from memory cells, as the object of test, addressed by these address signals.

Abstract: The present invention is a system and method that facilitates flexible restriction of output transmissions from chosen scan test cells and reduces adverse impacts on functional components from coincidental test vector values during scan test operations. The system and method of the present invention provides the capability of masking test vector values that coincidentally trigger certain undesirable events in functional components. In one embodiment, a system and method of the present invention masks test vector values shifted into scan test cells that are coupled to bus driver enabling signals. The system and method of the of the present invention also facilitates flexible selection of which scan test cell outputs are masked and permits a scan test cell to provide a scan test vector value to an associated functional component and prevent coincidental transmission of inappropriate test vector values.

Abstract: A technique to detect and correct corruption of instructions by soft errors. A parity bit is propagated with an instruction through the instruction flow path and checked at selected places. When a parity error is detected, a replay circuit is used to perform a replay to reload the instruction to remove the corrupted instruction.

Abstract: A method and apparatus for detecting disk drive head instability. Normal head fluctuation is removed from the criterion used to detect whether a head is unstable. The present invention accumulates error signals in an accumulator and calculates a criterion having an average fluctuation removed using the accumulated error signals. The criterion is calculated according to (max+min)−(2×average), wherein max is the maximum error signal, min is the minimum error signal and average is the average error signal. The criterion is then compared to a predetermine threshold to determine whether the head is unstable. A head is determined to be unstable when (max+min)−(2×average) is greater than the predetermined threshold.

Abstract: A semiconductor device comprising a memory circuit, a switch for relieving the memory circuit of its failures, and a logic circuit to be tested, facilitates a test of the logic circuit. When a switch control signal (SET) is “1”, for example, a switch (200) selects predetermined 1-bit data (=c) from a plurality of 1-bit data (=b) outputted in parallel form from a RAM (100) and outputs it to a logic circuit (300), where c<b.

Abstract: A data inspection method includes the steps of (a) writing original test data in a memory region, (b) reading the test data from the memory region, and (c) comparing the read test data with the original test data, so as to make a data inspection. The test data is formed by a plurality of cell data. Each of the cell data includes a delimiter indicating a boundary between two adjacent cell data, a cell number indicating an order within the test data, a cell data length indicating a data length of the cell data, and pattern data. Each of the cell data in the test data has a cell data length which is variable.