Abstract: The disclosure reduces the risk of collapse of the wall surrounding the trench and suppresses the withstand voltage fluctuation that accompanies the manufacturing variation for a semiconductor device having a super junction structure. The semiconductor device includes a drift layer of a first conductivity type and a plurality of embedded parts embedded in the drift layer. The embedded parts are of a second conductivity type different from the first conductivity type, and the embedded parts are arranged with a first direction as a longitudinal direction and spaced from each other along a second direction that intersects the first direction. A width of each of the embedded parts in the second direction changes continuously along the first direction.

Abstract: A light emitting apparatus is provided. The light emitting apparatus includes a frame structure having a bottom side and a reflective lateral side connecting to the bottom side; and a first light emitting element and a second light emitting element on the bottom side of the frame structure. The first light emitting element is configured to emit a first light having a first wavelength range along a first direction. The second light emitting element is configured to emit a second light having a second wavelength range along a second direction. The first direction and the second direction are substantially opposite to each other. The reflective lateral side of the frame structure is configured to reflect the first light having the first wavelength range into a first reflected light and reflect the second light having the second wavelength range into a second reflected light.

Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes a semiconductor substrate and an isolation structure over the semiconductor substrate. The semiconductor device structure also includes a first fin structure over the semiconductor substrate and surrounded by the isolation structure and a stack of nanostructures over the first fin structure. The nanostructures are separated from each other. The semiconductor device structure further includes a second fin structure over the semiconductor substrate. The second fin structure has an embedded portion surrounded by the isolation structure and a protruding portion over the isolation structure. The embedded portion is separated from the protruding portion by a distance.

Abstract: An organic light emitting diode (“OLED”) display device includes a substrate having a display region including a light emitting region and a peripheral region, and a pad region located in one side of the display region, a plurality of light emitting structures on the substrate in the light emitting region, and a plurality of fan-out wirings including a low fan-out wiring in the peripheral region on the substrate, a middle fan-out wiring on the low fan-out wiring, the middle fan-out wiring overlapping at least a portion of the low fan-out wiring, and an upper fan-out wiring on the middle fan-out wiring, the upper fan-out wiring overlapping at least a portion of the low fan-out wiring.

Abstract: An integrated circuit packaging method and an integrated packaging circuit, the integrated circuit packaging method including: circuit layers are provided on the top surface of a substrate, the bottom surface of the substrate or the interior of the substrate, the circuit layers having circuit pins; the substrate is provided with connection through holes, and the connection through holes are joined up with the circuit pins; a device is placed on the substrate, and the device is provided with device pins on a surface facing the substrate, which makes the device pins join up with a first opening of the connection through holes; conductive layers are fabricated in the connection through holes by means of a second opening of the connection through holes; and the conductive layers electrically connect the device pins to the circuit pins.

Abstract: An apparatus comprises an antifuse cell comprising first and second nodes, an antifuse element, and a transistor. The antifuse element and the transistor are coupled in series between the first and second nodes. The antifuse element comprises an antifuse gate. The transistor comprises a transistor gate comprising a substantially-annular structure substantially surrounding the antifuse gate.

Abstract: An optoelectronic module. In some embodiments, the optoelectronic module includes: a substrate; a digital integrated circuit, on an upper surface of the substrate; and a frame, secured in a pocket of the substrate. The pocket is in a lower surface of the substrate, and the substrate includes an insulating layer, and a plurality of conductive traces.

Abstract: An integrated circuit having a crack detection structure. A control structure is formed having interleaved electrically conductive layers and non electrically conductive layers in a vertical orientation. Electrically conductive vias are disposed vertically through all of the non electrically conductive layers, which vias electrically connect all of the electrically conductive layers one to another. A test structure is formed having a bonding pad for probing and bonding, with underlying interleaved electrically conductive layers and non electrically conductive layers disposed in a vertical orientation. At least one of the non electrically conductive layers has no vias formed therein, simulating active circuitry under other bonding pads of the integrated circuit. At least one of the interleaved electrically conductive layers of the control structure extends from within the control structure to within the test structure as a sensing layer.