Patents Examined by Matthew M. Kim
  • Patent number: 10387398
    Abstract: Execution of a page flusher is initiated in an in-memory database system in which pages are loaded into memory and which has associated physical disk storage. Thereafter, the page flusher identifies pages that were last modified outside a pre-defined time window. The page flusher then flushes the identified modified pages to the physical disk storage.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: August 20, 2019
    Assignee: SAP SE
    Inventors: Dirk Thomsen, Werner Thesing
  • Patent number: 10360111
    Abstract: Execution of a page flusher is initiated in an in-memory database system in which pages are loaded into memory and having associated physical disk storage by a resource flush thread using a queue. Thereafter, pages are identified that have been loaded into the memory of the database system and which have been modified. These identified pages are to be flushed to the physical disk storage. Each page is assigned with a different ordered physical page number. These identified pages are added to the queue. Subsequently, asynchronous write I/O is triggered causing the identified pages to be flushed to the physical disk storage and stored in the physical disk storage according to their assigned physical page numbers such that, if at least one predetermined performance condition is met, a subset of the identified pages in the queue are flushed to physical disk storage.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: July 23, 2019
    Assignee: SAP SE
    Inventor: Dirk Thomsen
  • Patent number: 10310946
    Abstract: Execution of a page flusher is initiated in an in-memory database system in which pages are loaded into memory and having associated physical disk storage. Thereafter, pages are identified that have been loaded into the memory of the database system and which have been modified. These identified pages are to be flushed to the physical disk storage. Each page is assigned with a different ordered physical page number. Asynchronous write I/O is later triggered causing the identified pages to be flushed to the physical disk storage and stored in the physical disk storage according to their assigned physical page numbers.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: June 4, 2019
    Assignee: SAP SE
    Inventor: Dirk Thomsen
  • Patent number: 10061670
    Abstract: An apparatus includes an input that receives a continuous function chart for each component of the investigated safety-critical system. A processor generates a corresponding component fault tree element. Inports and outports of the component fault tree element are generated and interconnected based on unique names of the inputs and outputs of the corresponding continuous function chart of the respective system component. Input failure modes and output failure modes are generated based on generic mapping between connector types of the continuous function chart and failure types of failure modes of the component fault tree element. The input failure modes of a component fault tree element are connected to output failure modes of the component fault tree element via internal failure propagation paths based on interconnected function blocks of the continuous function chart of the respective system component. An output outputs the generated component fault tree of the safety-critical system.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: August 28, 2018
    Assignee: Siemens Aktiengesellschaft
    Inventors: Kai Höfig, Marc Zeller
  • Patent number: 10055320
    Abstract: Data is replicated into a memory cache and cache inhibited memory in data segments with segment size that provides non-naturally aligned data boundaries to reduce the time needed to generate test cases for testing a processor. Placing data in the non-naturally aligned data boundaries allows replicated testing of the memory cache and cache inhibited memory while preserving double word and quad word boundaries in segments of the replicated test data. This allows test cases generated for cacheable memory to be replicated and used for cache inhibited memory. The processor can then use a single test replicated in this manner by branching back and using the next slice of the replicated test data in the memory cache and cache inhibited memory.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: August 21, 2018
    Assignee: International Business Machines Corporation
    Inventors: Manoj Dusanapudi, Shakti Kapoor
  • Patent number: 7404051
    Abstract: An apparatus, system, and method for replicating a snapshot volume in a first storage system to a second storage system includes mapping information corresponding to data in the first storage system that is transferred from the first storage system to the second storage system so that a file system in the second storage system can mount the data after replication. Replication of the snapshot volume can be accomplished using a remote copy mechanism. The snapshot volume can be obtained from a primary source volume P-VOL and a differential source volume D-VOL. If the corresponding destination volumes are not known, a search is conducted to locate appropriate volumes in the second storage system. Mapping information regarding these destination volumes is utilized to enable the file system in the second storage system to mount the replicated snapshot volume.
    Type: Grant
    Filed: April 18, 2005
    Date of Patent: July 22, 2008
    Assignee: Hitachi, Ltd.
    Inventor: Hidehisa Shitomi
  • Patent number: 7051169
    Abstract: The present invention provides a method and system that uses serial, writable, nonvolatile memory (serial memory) in a portable radio telephone. According to an object of the present invention, the serial memory may be integral to a cell phone or attached to a cell phone via an add-on card or the like. According to another object, the serial memory may be embedded in a cell phone accessory or attached to an accessory via an add-on card or the like. In both objects, once the portable radio telephone is powered on, data stored in serial memory is transferred into onboard random access memory (RAM), which in turn is utilized by the CPU and/or other cell phone systems. Serial memory includes, but is not limited to, NAND-type flash memory, as well as, flash and EEPROM memories that utilize the following interface architectures: the mircowire bus, the I2C bus, the SPI bus and/or the MPS bus. Among other things, serial memory may store the operating system, applications, and radio calibration parameters.
    Type: Grant
    Filed: February 26, 2002
    Date of Patent: May 23, 2006
    Assignee: Kyocera Wireless Corp.
    Inventor: Robert Bruce Ganton
  • Patent number: 6738885
    Abstract: An information capturing device (10) includes a controller (12) and a memory (14). The controller (12) partitions a memory space of the memory (14) into a plurality of memory blocks (20). The controller (12) controls the storage of received information into a first set (22) of the plurality of memory blocks (20). The controller (12) continues to store received information only in the first set (22) of the plurality of memory blocks (20) through reuse and recycle until a first triggering event occurs. In response to the first triggering event, the controller (12) halts the storage of received information in the first set (22) of the plurality of memory blocks (20) and begins storing received information in a second set (24) of the plurality of memory blocks (20). When the second set (24) of the plurality of memory blocks (24) has reached its storage capacity, the controller (12) begins storing received information in a third set (26) of the plurality of memory blocks (20).
    Type: Grant
    Filed: February 15, 2001
    Date of Patent: May 18, 2004
    Assignee: Silicon Graphics, Inc.
    Inventors: David X. Zhang, Kenneth C. Yeager, Steven T. Peltier
  • Patent number: 6457114
    Abstract: A memory controller for a special purpose digital video processor. To achieve a speed enhancement when using multiple bank memory such as SDRAM, the memory controller arbitrates requests for access to the memory such that, if possible, sequential memory accesses are directed to alternating memory banks. To facilitate access to contiguous blocks of memory such as are often accessed in video signal processing, the memory controller includes an address generator for generating multiple memory addresses in response to a single memory access request. The memory controller further includes features, which permit the use of multiple physical memory configurations. Specifically, the memory controller includes a memory address mapper for translating virtual memory address signals into physical memory address signals for address memory; for different memory configurations, the translation is different.
    Type: Grant
    Filed: February 22, 1999
    Date of Patent: September 24, 2002
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventor: Edward J. Paluch
  • Patent number: 6438645
    Abstract: A method and apparatus of reducing the time for enabling a dynamic random access memory (DRAM) upon initial application of power, comprises generating an internal RAS signal upon initial power up to generate internal voltages. The internal RAS pulse is asserted after a short time delay ends. After the internal RAS pulse is asserted, voltages on a digit line pair are amplified with a sense amplifier. Then, the amplified voltages on the digit line pair are equilibrated with an equilibration circuit. The equilibrated voltage is also coupled through the equilibration circuit to charge a common plate of a memory cell capacitor.
    Type: Grant
    Filed: July 31, 2000
    Date of Patent: August 20, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Stephen L. Casper
  • Patent number: 6438669
    Abstract: A non-volatile memory device that comprises an internal bus for the transmission of data and other information of the memory to output pads; a timer; and an enabling/disabling circuit for enabling and disabling access to the internal bus; the timer controlling the internal bus to transmit information signals of the memory device that originate from local auxiliary lines over the internal bus when the bus is in an inactive period during a normal memory data reading cycle; the timer controlling the enabling/disabling means to allow/deny access to the internal bus on the part of the information signals or of the data from or to the memory.
    Type: Grant
    Filed: March 7, 1997
    Date of Patent: August 20, 2002
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Luigi Pascucci, Paolo Rolandi, Marco Fontana, Antonio Barcella
  • Patent number: 6434665
    Abstract: Methods and an apparatus for storing information in a processing device with flexible security are disclosed. In one embodiment, an apparatus processes back-to-back write and read operations without stalling the processor. A cache memory subsystem buffers write operations between a central processing unit (CPU) and the cache memory subsystem. Included in the cache memory subsystem are a tag memory, a data memory and a store buffer. The store buffer is coupled to both the data memory and the tag memory. Additionally, the store buffer stores a write operation.
    Type: Grant
    Filed: October 1, 1999
    Date of Patent: August 13, 2002
    Assignee: STMicroelectronics, Inc.
    Inventors: David Shepherd, Rajesh Chopra
  • Patent number: 6412059
    Abstract: In order to immediately respond to an access request from a processor with reduced power consumption, a requested information is read out from a cache memory 31 or information buffers 421 to 421 and supplied to the processor when comparators 343 to 3410 output hit signals.
    Type: Grant
    Filed: October 1, 1999
    Date of Patent: June 25, 2002
    Assignee: NEC Corporation
    Inventor: Hideki Matsuyama
  • Patent number: 6397291
    Abstract: A data retrieval system receives a data address identifying data to be retrieved. A portion of the received data address is communicated to a data storage device during a first clock cycle. The system determines a second address portion based on the received data address. The second address portion is communicated to the data storage device during a second clock cycle. Data is then retrieved from the data storage device based on the address portions communicated to the data storage device. The portion of the received data address communicated to the data storage device during the first clock cycle is a set address and the second address portion communicated to the data storage device during the second clock cycle is a way address. A read cycle can be initiated after communicating a portion of the received data address to the data storage device during the first clock cycle.
    Type: Grant
    Filed: December 5, 2000
    Date of Patent: May 28, 2002
    Assignee: Intel Corporation
    Inventors: Randy M. Bonella, Peter D. MacWilliams, Konrad K. Lai
  • Patent number: 6393525
    Abstract: An LRU with protection method is provided that offers substantial performance benefits over traditional LRU replacement methods by providing solutions to common problems with traditional LRU replacement. By dividing a cache entry list into a filter sublist and a reuse list, population and protection processes can be implemented to reduce associativity and capacity displacement. New cache entries are initially stored in the filter list, and the reuse list is populated with entries promoted from the cache list. Eviction from the filter list and reuse list is done by a protection process that evicts a data entry from the filter, reuse, or global cache list. Many variations of protection and eviction processes are discussed herein, along with the benefits each provides in reducing the effect of unwanted displacement problems present in traditional LRU replacement.
    Type: Grant
    Filed: May 18, 1999
    Date of Patent: May 21, 2002
    Assignee: Intel Corporation
    Inventors: Christopher B. Wilkerson, Nicholas D. Wade
  • Patent number: 6393512
    Abstract: A bank conflict detector compares at least a portion of a current address signal (i.e. an address signal generated by a request currently issued to main memory) with a corresponding portion of a to-be-issued memory address signal, to determine if a bank conflict exists. Specifically, in one embodiment, the bank conflict detector includes a number of exclusive OR gates that receive as inputs the two addresses to be compared, and generate an output (also called “XOR result”) that is compared with predetermined patterns to determine if a bank conflict exists. For example, if the bank conflict detector finds that the XOR result is 0 (zero) then the two addresses access the same bank. The bank conflict detector also the XOR result with patterns that are formed by a number of consecutive 1s in the least significant bits and a number of consecutive 0s in the most significant bits. If no match, then the bank conflict detector determines that no bank conflict exists.
    Type: Grant
    Filed: September 27, 1999
    Date of Patent: May 21, 2002
    Assignee: ATI International SRL
    Inventors: Andrea Y. J. Chen, Lordson L. Yue
  • Patent number: 6393534
    Abstract: A main memory scheduler includes a store, and stores therein requests for accessing main memory (such as a read request, a write request, or a refresh request). Normally, the main memory scheduler issues requests from the store to the main memory in an order different from the order in which the requests are received, for example, to avoid bank conflicts. In this example, the main memory scheduler issues a first request to a first memory bank that is not coincident with (and in case of dependent banks, not adjacent to) a second memory bank (that is being currently accessed) prior to issuing a second request to a memory bank that is coincident with the (or adjacent to) second memory bank. Moreover, the main memory scheduler issues a refresh request prior to issuing a read request or a write request even if the refresh request was most recently received, thereby to prioritize the refresh request ahead of read and write requests.
    Type: Grant
    Filed: September 27, 1999
    Date of Patent: May 21, 2002
    Assignee: ATI International SRL
    Inventors: Andrea Y. J. Chen, Lordson L. Yue
  • Patent number: 6385696
    Abstract: A processor having an embedded cache memory, the cache including a tag array that is split into first and second halves each having N ways, the first half storing an upper M sets and the second half storing a lower M sets. Lower order linear address bits read the first and second halves in a first phase of a clock cycle. Compare circuitry compares each of the N ways read out of both the first and second halves of the tag array with higher order physical address bits. Select circuitry then selects one of two sets of way select signals based on a higher order linear address bit. A data array having N ways and 2M sets is accessed by the lower order linear address bits in combination with the higher order linear address bit, with the selected set of way select signals outputting data of the correct way.
    Type: Grant
    Filed: June 25, 1999
    Date of Patent: May 7, 2002
    Assignee: Intel Corporation
    Inventor: Jack D. Doweck
  • Patent number: 6385706
    Abstract: Method and apparatus for restoring copies of a logical object to a primary computer storage device are disclosed. A copy of the logical object is provided, physical blocks of memory in the primary storage device are allocated, a map of the data blocks will be copied to the physical blocks of the primary storage devices created. The copying may then occur using the created map. The copy of the logical object may be an abstract bloc set, which includes data blocks of the logical object potentially out of order and metadata identifying relative position of the data blocks.
    Type: Grant
    Filed: December 31, 1998
    Date of Patent: May 7, 2002
    Assignee: EMX Corporation
    Inventors: Yuval Ofek, Zoran Cakeljic, Philip Tamer
  • Patent number: 6378065
    Abstract: The present invention relates to a data processing unit, comprising at least one register having at least one read port and one write port. The register has at least two memory cells each having a write line and a read line, a first switch having inputs and one output for coupling said read line of one of said memory cells with said read port, second switch for coupling said write line of one of said memory cells with said write port.
    Type: Grant
    Filed: April 27, 1998
    Date of Patent: April 23, 2002
    Assignee: Infineon Technologies North America Corp.
    Inventors: Roger D. Arnold, Alfred Eder