Abstract: Provides load balancing, recovery and reconfiguration control for a data move subsystem comprised of a plurality of interconnected and cooperating data move processors (DMPs). Each DMP processor has an associated queue for receiving queue elements (QEs) from central processing units of a data processing system which specify data move requirements of the data processing system. QEs can be transferred between queues of other DMPs or a common queue to achieve load balancing, recovery and reconfiguration control.

Abstract: An apparatus for enabling an object-oriented application to access in an object-oriented manner a procedural operating system having a native procedural interface is disclosed. The apparatus includes a computer and a memory component in the computer and support for a host system. A code library is stored in the memory component. The code library includes computer program logic implementing an object-oriented class library. The object-oriented class library comprises related object-oriented classes for enabling the application to access in an object-oriented manner services provided by the operating system. The object-oriented classes include methods for accessing the operating system services using procedural function calls compatible with the native procedural interface of the operating system. The computer processes object-oriented statements contained in the application and defined by the class library by executing methods from the class library corresponding to the object-oriented statements.

Abstract: The present invention provides a system and method for optimizing or parallelizing computer code typically represented by a source program. The source program is represented by a control flow graph. The present invention includes an optimizer for constructing a compact data flow representation from the control flow graph and a mechanism for evaluating the compact data flow representation in relation to a data flow framework in order to determine a solution to a particular data flow problem. The present invention represents data flow chains compactly, obtaining some of the advantages of Static Single Assignment (SSA) form without modification of program text (i.e., renaming). In addition, the present invention represents compactly certain data flow chains which SSA form fails to represent (i.e. def-def, use-def, and use-use chains).

Abstract: A hardware timer dedicated to the BIOS which operates independent of the CPU timer. The BIOS activates the timer by writing a delay count to a predetermined port. Address decode circuitry identifies an address match to a write port address. When an address match coincides with a write command from the BIOS, write control circuitry coupled to the address decode circuitry activates a "load" signal for loading the delay count into a counter circuit. The counter circuit, which is coupled to the write control circuitry, operates on a clock having frequency independent of the CPU operating frequency. The counter circuit comprises a flip-flop that synchronizes the "load" signal to the clock of the counter circuit. The synchronized "load" signal causes the delay count to be loaded into the counter circuit. The write control circuitry inactivates the "load" signal such that the delay count is loaded exactly once. The counter circuit counts when the synchronized "load" signal is inactive.

Abstract: A context switching system for saving, restoring or swapping tasks, and is adapted for use in a multitasking processor coupled to an external or system memory. The processor includes one or more functional blocks to perform the tasks. The functional blocks comprise registers that store state data that, at a particular instant, represents the context of the system. The system comprises a controller that receives a save or switch command and generates a context save instruction in response thereto. The controller is configured to pass the context save instruction to the functional blocks. The functional blocks generate a state program. The state program comprises one or more register load instructions and the state data representing the context of the system so that context can be restored at a later time. The state program is stored in an external or system memory. Saving context as state programs permits the system to quickly switch from one context to another without losing important information.

Abstract: A configuration builder provides a common user interface for configuring a variety of different software components. The configuration builder consists of a number of component-specific builder modules and a generic user interface module. Each builder module contains templates defining user screens for inputting configuration information for a component, as well as validation rules and error messages. The configuration data for a component is obtained as set of tables, each containing records, and is then translated into the actual configuration file for use by the component.

Abstract: Extremely localized parse rules, dependent only upon either intrinsic characteristics of each packet or upon transitions in characteristics between consecutive pairs or triples of packets, give a determinable fragmentation of an information stream which is relatively insensitive to imbedded error, insertion or deletion. Iterative application of such parsing on the stream of parsed fragments produces a corresponding hierarchy of levels of fragments of increasing length. The highest level fragments are matched to a dictionary or history, tokenized and presented for output to form a compressed data stream.

Abstract: A restriction checker generator is disclosed for generating a restriction checker capable of checking horizontal microcode instructions against restrictions which the microcode instructions must satisfy in order to be valid. The generator comprises means for transforming information representing each restriction into at least one logical test for the instruction, each logical test comprising a number of sub-tests for the values of fields of the instruction such that failure of any one of the sub-tests by an instruction indicates that the restriction is satisfied by the instruction. The sub-tests can be set-membership tests or arithmetic tests.

Abstract: An apparatus for enabling an object-oriented application to access in an object-oriented manner a procedural operating system having a native procedural interface is disclosed. The apparatus includes a computer and a memory component in the computer. A code library is stored in the memory component. The code library includes computer program logic implementing an object-oriented class library. The object-oriented class library comprises related object-oriented classes for enabling the application to access in an object-oriented manner services provided by the operating system. The object-oriented classes include methods for accessing the operating system services using procedural function calls compatible with the native procedural interface of the operating system. The computer processes object-oriented statements contained in the application and defined by the class library by executing methods from the class library corresponding to the object-oriented statements.

Abstract: A data processing apparatus and method are described in which a CPU is operable in either a main processing mode (User32) or an exception processing mode (e.g. FIQ32). The CPU has a plurality of main data registers (R0 to R15) and a processing status register (CPSR) for use in the main processing mode. Upon entering the exception processing mode at least one exception data register (R8fiq to R14fiq) is substituted for use in place of a respective corresponding one of the main data registers and the data held within the processing status register is stored within a saved processing status register (SPSRfiq). When the exception processing mode is left, the main data registers are returned for use in place of the exception data registers and the data stored within the saved processing status register is restored to the processing status register. A plurality of exception processing modes are described each having their own associated exception data registers.

Abstract: In contrast to previous methods, for example for LISP systems, a central function caller with its complex status inquiries is not required, since a data structure with a link header is provided, to which directly executable execution code is always chained. Depending on the type of function and depending on the respective status of a definition of the program element, it is possible to provide here as execution code an error interface for undefined functions, a simulator interface for functions to be simulated, an interpreter interface for functions to be interpreted or a compiled program section for already compiled functions. As a result of dispensing with the status inquiries, it is possible to achieve considerable acceleration of the program execution, in particular for LISP systems, in which a function call often occurs for usually only short function operations.

Abstract: An apparatus for enabling an object-oriented application to access in an object-oriented manner a procedural operating system having a native procedural interface is disclosed. The apparatus includes a computer and a memory component in the computer. A code library is stored in the memory component. The code library includes computer program logic implementing an object-oriented class library. The object-oriented class library comprises related object-oriented classes for enabling the application to access in an object-oriented manner services provided by the operating system. The object-oriented classes include methods for accessing the operating system services using procedural function calls compatible with the native procedural interface of the operating system. The computer processes object-oriented statements contained in the application and defined by the class library by executing methods from the class library corresponding to the object-oriented statements.

Abstract: A method and system for dynamically scheduling the building of computer programs from source code parts which may have dependencies which require that some parts be compiled before others. A list of source code parts and dependencies is dynamically created as compilation of the parts is attempted. The build status for each part is tracked. The list is repeatedly processed until none of the build status fields changes during an entire pass through the list. The source code parts which cannot be compiled and integrated in the build for reasons such as circular compilation dependencies or references to non-existing, prerequisite source code parts will be identified by this process.

Abstract: A scheduler for scheduling communication by a plurality of clients who compete to use a shared resource. Each client asserts a request bit to request use of the shared resource, and receives a grant bit from the scheduler that is asserted when the client is scheduled to use the shared resource. The scheduler includes a SC generation unit in which the request bits are inverted, the bit at the previous scheduling cycle grant is forced, and a scheduler carry operation is performed on the inverted request bits and grant bits to supply carry bits. The carry bits are "AND"ed with the forced, inverted request bits to supply a SC result and a carryout bit. The carryin bit is initially assumed to be zero, and the SC generation unit performs an initial operation. If the carryout bit from the final generation unit is zero, then the SC result bits for the initial operation provide the .grant word for the current scheduling cycle.

Abstract: The invention disclosed herein is a system and method for comprehensive, non-invasive profiling of a processor whereby feedback is provided to a programmer of the execution dynamics of a program. In a preferred embodiment a partial real-time reduction is provided of selected trace events employing the environment's trace facility, and a post-processing function is then performed. A trace hook is provided in the environment's periodic clock routine which captures the address to be returned to following this timer's interrupt, and further captures the address of the caller of the routine represented by the first address. The frequency of occurrences of the first address is collected and correlated to various virtual address spaces and corresponding subroutine offsets within those virtual address spaces.

Abstract: A modularly-structured integrated services digital network (ISDN) communication system comprises a system processor that should be available for a real-time operating system and for a timesharing operating system. In order to enable continuous transitions of the system processor from one operating system into the other operating system, the task having the lowest priority (idle task) and a program subsystem having comparatively high priority in the real-time operating system (multitasking operating system) are fashioned as branch subsystems in which an assignment change from the addressing tables of the real-time operating system onto that of the timesharing operating system occur. The program subsystem with comparatively high priority which is fashioned as a branch subsystem assures that a certain minimum portion of the calculating capacity of the system processor is assigned to the timesharing operating system independently of the traffic load of the real-time operating system.