Abstract: Circuits for generating multiple clocks for computer systems are disclosed. One such system includes a circuit configured to generate a core clock, a system bus clock, and a peripheral clock. The frequency of one of the clocks can be reduced or altered without altering the frequencies at which the other clocks oscillate. Also disclosed are methods for incorporating or utilizing the disclosed circuits.
Abstract: An information processing apparatus includes a processor, and a detector to detect the operation clock frequency set for a unit connected to a bus. The frequency of a clock to be supplied from the processor is set in accordance with the detected clock frequency.
© 2024 Justia
