Patents Examined by Matthew S. Smith
  • Patent number: 10394227
    Abstract: In one embodiment, a multi-purpose sensor may couple to a machine operating in an industrial environment and include numerous sensors disposed within the multi-purpose sensor to acquire sets of data associated with the machine or an environment surrounding the machine. A first portion of the sets of data may include historical sensor measurements over time for each of the sensors, and a second portion of the sets of data may include sensor measurements subsequent to when the first portion is acquired for each of the sensors. A processor of the multi-purpose sensor may determine a baseline collective signature based on the first portion, determine a subsequent collective signature based on the second portion, determine whether the collective signatures vary, and generate signals when a variance exists. The signals may cause a computing device, a cloud-based computing system, and/or a control/monitoring device to perform various actions.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: August 27, 2019
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Jimi R. Michalscheck, Kelly A. Michalscheck, Jessica L. Korpela, Kyle K. Reissner, David A. Vasko, Matthew W. Fordenwalt, John J. Jauquet, Matthew R. Ericsson, Andrew Wilber
  • Patent number: 10344358
    Abstract: A method, device and article of manufacture for determining properties in a high pressure die cast component. Upon receipt of geometric information that corresponds to a location of interest within the component, a ray-triangle intersection relationship is used to calculate a wall thickness of the location of interest; this relationship is simplified by being used in conjunction with an octree-based relationship. One or more calculations are performed to determine a skin thickness based on the calculated wall thickness, and the skin thickness calculations are based on at least one of a logarithmic relationship, a polynomial relationship and a power law relationship. Changes in component shape or size may be taken into consideration to adjust the remaining skin layer thickness, such as that when the as-cast component is exposed to subsequent machining or related post-casting operations.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: July 9, 2019
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Qigui Wang, Bing Li, Cherng-Chi Chang, Wenying Yang, Michael J. McCreedy
  • Patent number: 7968386
    Abstract: Application form of and demand for an IC chip formed with a silicon wafer are expected to increase, and further reduction in cost is required. An object of the invention is to provide a structure of an IC chip and a process capable of producing at a lower cost. In view of the above described object, one feature of the invention is to provide the steps of forming a separation layer over an insulating substrate and forming a thin film integrated circuit having a semiconductor film as an active region over the separation layer, wherein the thin film integrated circuit is not separated. There is less limitation on the shape of a mother substrate in the case of using the insulating substrate, when compared with the case of taking a chip out of a circular silicon wafer. Accordingly, reduction in cost of an IC chip can be achieved.
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: June 28, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Koji Dairiki
  • Patent number: 7964474
    Abstract: A method includes growing a first oxide region concurrently with a second oxide region in a substrate and forming an inlet path to the first oxide region, the inlet path exposing a first surface of the first oxide region. The method also includes removing the first oxide region to form a chamber, forming a first MOS transistor adjacent the second oxide region, and forming a second MOS transistor separated from the first MOS transistor by the second oxide region.
    Type: Grant
    Filed: April 13, 2009
    Date of Patent: June 21, 2011
    Assignee: STMicroelectronics, Inc.
    Inventors: Ming Fang, Fuchao Wang
  • Patent number: 7964417
    Abstract: A method of measuring a degree of crystallinity of a polycrystalline silicon substrate includes obtaining a Raman spectrum graph by irradiating a polycrystalline silicon substrate with a laser beam; and calculating a degree of crystallinity of the polycrystalline silicon substrate from the Raman spectrum graph using the following formula: (degree of crystallinity)=(area of polycrystalline peak)/[(area of amorphous peak)+(area of polycrystalline peak)].
    Type: Grant
    Filed: November 6, 2006
    Date of Patent: June 21, 2011
    Assignee: Samsung Mobile Display Co., Ltd.
    Inventor: Hong-Ro Lee
  • Patent number: 7964928
    Abstract: A photodetector made in monolithic form in a lightly-doped substrate of a first conductivity type. This photodetector includes at least two photodiodes and includes a first region of the first conductivity type more heavily doped than the substrate extending at least between the two photodiodes; and a second region of the first conductivity type more heavily doped than the substrate and extending under the first region and under one of the two photodiodes, the first region or the second region, with the first region, delimiting a substrate portion at the level of said one of the two photodiodes, and the second region, with the first region, delimiting an additional substrate portion at the level of the other one of the two photodiodes.
    Type: Grant
    Filed: November 20, 2006
    Date of Patent: June 21, 2011
    Assignee: STMicroelectronics S.A.
    Inventors: Fran├žois Roy, Thomas Girault, Yann Marcellier, Caroline Bringolf-Penner
  • Patent number: 7964490
    Abstract: Embodiments of the present invention describe a method of forming nickel sulfide layer on a semiconductor device. A nickel sulfide layer is formed on a substrate by alternatingly exposing the substrate to a nickel-containing precursor and a sulfur-containing precursor.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: June 21, 2011
    Assignee: Intel Corporation
    Inventors: Scott Bruce Clendenning, Niloy Mukherjee, Ravi Pillarisetty
  • Patent number: 7964471
    Abstract: A method of forming a capacitor includes providing material having an opening therein over a node location on a substrate. A shield is provided within and across the opening, with a void being received within the opening above the shield and a void being received within the opening below the shield. The shield is etched through within the opening. After the etching, a first capacitor electrode is formed within the opening in electrical connection with the node location. A capacitor dielectric and a second capacitor electrode are formed operatively adjacent the first capacitor electrode.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: June 21, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Mark Kiehlbauch, Kevin R. Shea
  • Patent number: 7964893
    Abstract: A method of forming an electrostatic discharging (ESD) device includes forming a first and a second semiconductor fin over a substrate and adjacent to each other; epitaxially growing a semiconductor material on the first and the second semiconductor fins, wherein a first portion of the semiconductor material grown from the first semiconductor fin joins a second portion of the semiconductor material grown from the second semiconductor fin; and implanting a first end and a second end of the semiconductor material and first end portions of the first and the second semiconductor fins to form a first and a second implant region, respectively. A P-N junction is formed between the first end and the second end of the semiconductor material. The P-N junction is a junction of an ESD diode, or a junction in an NPN or a PNP BJT.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: June 21, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jam-Wem Lee
  • Patent number: 7964462
    Abstract: Provided is a method of manufacturing a semiconductor device. The method includes: forming a charge storage layer on a substrate on which a gate insulating layer is formed; forming a first metal oxide layer on the charge storage layer using a first reaction source including a metal oxide layer precursor and a first oxidizing agent and changing the first metal oxide layer to a second metal oxide layer using a second reaction source including a second oxidizing agent having larger oxidizing power than the first oxidizing agent and repeating the forming of the first metal oxide layer and the changing of the first metal oxide layer to the second metal oxide layer several times to form a blocking insulating layer; and forming an electrode layer on the blocking insulating layer.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: June 21, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-chul Yoo, Han-mei Choi, Kwang-hee Lee, Kyong-won An, Cha-young Yoo
  • Patent number: 7960247
    Abstract: Microelectronic dies are thinned according to a variety of approaches, which may include bonding the dies to a substrate under vacuum, disposing a film over the dies and the substrate, and/or changing a center of pressure during thinning.
    Type: Grant
    Filed: April 4, 2008
    Date of Patent: June 14, 2011
    Assignee: The Charles Stark Draper Laboratory, Inc.
    Inventors: Jeffrey C. Thompson, Gary B. Tepolt, Livia M. Racz
  • Patent number: 7960261
    Abstract: The present invention relates to a method for manufacturing a polycrystalline semiconductor film that can be used for a semiconductor device. In the method, an amorphous semiconductor film is irradiated with a femtosecond laser to be crystallized. By laser irradiation using a femtosecond laser, when an amorphous semiconductor film over which a cap film is formed is crystallized with a laser, it becomes possible to perform crystallization of the semiconductor film and removal of the cap film at the same time. Therefore, a step of removing the cap film in a later step can be omitted.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: June 14, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Takatsugu Omata
  • Patent number: 7960235
    Abstract: A method for manufacturing a bulk Si nanometer surrounding-gate MOSFET based on a quasi-planar process, including: local oxidation isolation or shallow trench isolation; depositing buffer SiO2 oxide layer/SiN dielectric layer on the bulk Si; electron beam exposure; etching two adjacent slots; depositing SiN sidewalls; isotropically etching Si; dry oxidation; removing SiN by wet etching; forming the nanowire by stress self-constraint oxidation; depositing and anisotropically etching oxide dielectric layer and planarizing surface; releasing the nanowire by wet etching while keeping sufficiently thick SiO2 at bottom as isolation; growing gate dielectric and depositing gate material; etching back the gate and isotropically etching the gate material by using the gate dielectric as a block layer; shallow implantation in the source/drain region; depositing and etching sidewalls; deep implantation in the source/drain region to form contact.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: June 14, 2011
    Assignee: Institute of Microelectronics, Chinese Academy
    Inventors: Yi Song, Huajie Zhou, Qiuxia Xu
  • Patent number: 7960226
    Abstract: On-chip decoupling capacitor structures, and methods of fabricating such decoupling capacitors are disclosed. On-chip decoupling capacitors help to reduce or prevent L di/dt voltage droop on the power grid for high surge current conditions. The inclusion of one or more decoupling capacitors on a chip, in close proximity to the power grid conductors reduces parasitic inductance and thereby provides improved decoupling performance with respect to high frequency noise. In one embodiment of the present invention, a capacitor stack structure is inserted between metal interconnect layers. Such a capacitor stack may consist of a bottom electrode/barrier; a thin dielectric material having a high dielectric constant; and a top electrode/barrier. In an alternative embodiment, the bottom electrode and/or bottom metal interconnect layer have three dimensional texture to increase the surface area of the capacitor.
    Type: Grant
    Filed: December 23, 2005
    Date of Patent: June 14, 2011
    Assignee: Intel Corporation
    Inventors: Bruce A. Block, Richard Scott List, Ruitao Zhang
  • Patent number: 7956360
    Abstract: A method of growing highly planar, fully transparent and specular m-plane gallium nitride (GaN) films. The method provides for a significant reduction in structural defect densities via a lateral overgrowth technique. High quality, uniform, thick m-plane GaN films are produced for use as substrates for polarization-free device growth.
    Type: Grant
    Filed: April 6, 2007
    Date of Patent: June 7, 2011
    Assignees: The Regents of the University of California, Japan Science and Technology Agency
    Inventors: Benjamin A. Haskell, Melvin B. McLaurin, Steven P. DenBaars, James Stephen Speck, Shuji Nakamura
  • Patent number: 7955961
    Abstract: A trench-type Schottky semiconductor device and a method for fabricating the trench-type Schottky semiconductor device are disclosed. The method includes the steps of forming an epitaxial (EPI) layer atop a silicon substrate, forming a nitride layer atop the EPI layer, patterning a plurality of windows in the nitride layer into an active region and a termination region, forming a plurality of trenches in the active and termination regions such that the plurality of trenches in the termination regions are spaced apart from each other so as to form a plurality of mesas, lining the first type of trenches with a gate oxide layer, and converting the mesas to oxide mesas; and then applying a barrier layer metal to the mesas in the device active area and in the termination trenches.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: June 7, 2011
    Assignee: International Rectifier Corporation
    Inventor: Giovanni Richieri
  • Patent number: 7955960
    Abstract: A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: June 7, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Se Jun Kim, Eun Seok Choi, Kyoung Hwan Park, Hyun Seung Yoo, Myung Shik Lee, Young Ok Hong, Jung Ryul Ahn, Yong Top Kim, Kyung Pil Hwang, Won Sic Woo, Jae Young Park, Ki Hong Lee, Ki Seon Park, Moon Sig Joo
  • Patent number: 7951691
    Abstract: In a method for producing a thin film chip including an integrated circuit, a semi-conductor wafer having a first surface is provided. At least one cavity is produced under a defined section of the first surface by means of porous silicon. A circuit structure is produced in the defined section. The defined wafer section is subsequently released from the semiconductor wafer by severing local web-like connections, which hold the wafer section above the cavity and on the remaining semiconductor wafer.
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: May 31, 2011
    Assignee: Institut fuer Mikroelektronik Stuttgart
    Inventors: Joachim N. Burghartz, Martin Zimmermann, Wolfgang Appel
  • Patent number: 7951720
    Abstract: Forming contact holes of a semiconductor device includes forming a reaction layer that is provided with a reaction pattern on a semiconductor substrate. Subsequently, a self-assembled monolayer is formed by injecting a polymer from a functional group that is capable of being chemically bonded to the reaction pattern. A coating layer is then formed on substantially all of the structure that includes the self-assembled monolayer. Afterwards, the contact holes are formed on the semiconductor substrate by performing an etching process.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: May 31, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jun Hyung Park, Ki Sung Kwon
  • Patent number: 7952165
    Abstract: A heterojunction bipolar transistor structure with self-aligned sub-lithographic extrinsic base region including a self-aligned metal-semiconductor alloy and self-aligned metal contacts made to the base is disclosed. The lateral dimension of the extrinsic base region is defined by the footprint of a sacrificial spacer, and its thickness is controlled by selective epitaxy. A self-aligned semiconductor-metal alloy and self-aligned metal contacts are made to the extrinsic base using a method compatible with conventional silicon processing.
    Type: Grant
    Filed: January 10, 2007
    Date of Patent: May 31, 2011
    Assignee: International Business Machines Corporation
    Inventors: Guy M. Cohen, Francois Pagette