Abstract: Apparatus and method for generating random numbers. In accordance with some embodiments, the apparatus comprises a random number generator circuit that generates a random number responsive to a total number of programming pulses used to transition a solid-state memory cell from a first programming state to a second programming state.

Abstract: To obtain a high-quality enhanced signal, disclosed is a signal processing apparatus including a transform unit that transforms a mixed signal in which a first signal and a second signal coexist, into a phase component and a magnitude component or power component for each frequency, a first control unit that replaces the phase component of a predetermined frequency, a second control unit that modifies the magnitude component or power component of the predetermined frequency in accordance with the amount of a change of the magnitude component or power component that arises from replacement by the first control unit, and a reconstruction unit that reconstructs the phase component replaced by the first control unit and the magnitude component or power component modified by the second control unit.

Abstract: Asynchronous arithmetic units including an asynchronous IEEE 754 compliant floating-point adder and an asynchronous floating point multiplier component. Arithmetic units optimized for lower power consumption and methods for optimization are disclosed.

Abstract: A system is described for generating random numbers. The system may include a plurality of information sources and one or more sampling devices coupled to each of the information sources. Each information source may have a characteristic which may differ from the characteristic of any other information source. The sampling devices may sample the information sources at some sampling interval. A sample value may be captured from each of the information sources by the sampling devices coupled thereto at the sampling interval. An output representative of a substantially random number may be derived from the sample values captured at the sampling interval.

Abstract: This invention is a digital signal processor capable of performing correlation of data with pseudo noise for code division multiple access (CDMA) decoding using clusters. Each cluster includes plural multipliers. The multipliers multiply real and imaginary parts of packed data by corresponding pseudo noise data. Within a cluster the real parts and the imaginary parts of the products are summed separately. This forms plural complex number outputs equal in number to the number of clusters. The pseudo noise data is offset relative to the data input differing amounts for different clusters. The clusters are divided into first half clusters receiving data from even numbered slots and second half clusters receiving data from odd numbered slots. The correlation unit includes a mask input to selectively zero a multiplier product.

Abstract: According to one embodiment of the present invention, a system for compressing data determines a common divisor for a set of values comprising integers. The system divides each value within the set of values by the common divisor to produce reduced values, and represents the set of values in the form of data indicating the common divisor and the reduced values. Embodiments of the present invention further include a method and computer program product for compressing data in substantially the same manners described above.

Abstract: Digital signal processing (“DSP”) block circuitry on an integrated circuit (“IC”) is adapted for use, e.g., in multiple instances of the DSP block circuitry on the IC, for implementing finite-impulse-response (“FIR”) filters that are dynamically adjustable. Advantages of such DSP block circuitries may include an increase in performance and a reduction in logic and memory usage for multi-standard FIR filters.

Abstract: Computational techniques for mapping a continuous variable objective function into a discrete variable objective function problem that facilitate determining a solution of the problem via a quantum processor are described. The modified objective function is solved by minimizing the cost of the mapping via an iterative search algorithm.

Abstract: A method for processing linear systems of equations and finding a nx1 vector x satisfying Ax=b where A is a symmetric, positive-definite nxn matrix corresponding to nxn predefined high-precision elements and b is an n1 vector corresponding to n predefined high-precision elements. A first iterative process generates n low-precision elements corresponding to an nx1 vector x1 satisfying A1x1=b1 where A1, b1 are elements in low precision. The elements are converted to high-precision data elements to obtain a current solution vector x. A second iterative process generates n low-precision data elements corresponding to an nx1 correction vector dependent on the difference between the vector b and the vector product Ax. Then there is produced from the n low-precision data elements of the correction vector respective high-precision data elements of an nx1 update vector u. The data elements of the current solution vector x are updated such that x=x±u.

Abstract: The described system and method uses data from interaction between a known wave and an unknown wave to analyze or characterize the unknown wave using cross correlation frequency resolved optical gating (X-FROG). The system may obtain X-FROG trace data from the interaction between the two waves. The system analyzes the X-FROG trace data using a modified principal component generalized projection method strategy to invert the X-FROG trace data, analyzing or characterizing the unknown wave. Results of the analysis can be provided in real time and displayed.

Abstract: A method for generating a design of a multiplier is disclosed. The method generally includes steps (A) to (C). Step (A) may generate a first circuit comprising a plurality of polynomial results of a particular multiplier scheme based on a plurality of parameters of the multiplier. The first circuit is generally configured to multiply a plurality of polynomials. Step (B) may generate a second circuit comprising a plurality of polynomial evaluators based on the parameters. The second circuit may be (i) connected to the first circuit and (ii) configured to evaluate a polynomial modulo operation. Step (C) may generate the design of the multiplier in combinational logic by optimizing a depth of a plurality of logic gates through the first circuit and the second circuit. A product of the polynomials generally resides in a finite field.

Abstract: A circuit arrangement provides support for packed sum of absolute difference operations in a floating point execution unit, e.g., a scalar or vector floating point execution unit. Existing adders in a floating point execution unit may be utilized along with minimal additional logic in the floating point execution unit to support efficient execution of a fixed point packed sum of absolute differences instruction within the floating point execution unit, often eliminating the need for a separate vector fixed point execution unit in a processor architecture, and thereby leading to less logic and circuit area, lower power consumption and lower cost.

Abstract: Embodiments include methods of tuning state variable filters. Examples include state variable filters whose center frequencies can be tuned using variable gain blocks coupled to outputs of filter integrators. First- and second-order state variable filters may operate on signals in parallel and their outputs combined to produce a filtered output. Filters may be tuned to pass or reject signals depending on the application; sample applications include, but are not limited to: agile filtering; spectrum analysis; interference detection and rejection; equalization; direct intermediate-frequency transmission; and single-sideband modulation and demodulation.

Abstract: A method provides support for packed sum of absolute difference operations in a floating point execution unit, e.g., a scalar or vector floating point execution unit. Existing adders in a floating point execution unit may be utilized along with minimal additional logic in the floating point execution unit to support efficient execution of a fixed point packed sum of absolute differences instruction within the floating point execution unit, often eliminating the need for a separate vector fixed point execution unit in a processor architecture, and thereby leading to less logic and circuit area, lower power consumption and lower cost.

Abstract: Methods, computer systems, and computer program products for calculating a remainder by division of a sequence of bytes interpreted as a first number by a second number are provided. A first subset of bytes is read, and an associated first remainder by division is calculated and stored in the memory location from which the subset was read. A second subset of bytes is read, and an associated second remainder by division is calculated with a second processor. The calculating of the second remainder by division may occur at least partially during the calculating of the first remainder by division. A third and fourth subset of bytes is read and associated remainders are calculated.

Abstract: Disclosed herein are systems and methods for a signed-magnitude adder based on one's complement logic, where the adder offers enhancements in both speed and chip area consumption. The one's complement based adder includes circuitry for converting operands from their signed-magnitude representations to their one's complement representations, circuitry for adding operands in their one's complement representations, and circuitry for converting the resulting sum into a signed-magnitude format.

Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a Boolean logic circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A quantum processor may include multiple sets of qubits, each set coupled to respective annealing signal lines such that dynamic evolution of each set of qubits is controlled independently from the dynamic evolutions of the other sets of qubits.

Abstract: A method of identifying a set of parameters representative of a data set is provided. An eigen decomposition of a covariance matrix is calculated to form a decomposed matrix and an eigenvalue vector. The covariance matrix is calculated for a matrix of data including a plurality of data values for each of a plurality of parameters. The decomposed matrix includes a number of eigenvectors equal to a number of the plurality of parameters with each eigenvector including a coefficient for each parameter. The eigenvalue vector includes an eigenvalue defined for each eigenvector. A first matrix is created by rank ordering the coefficient within each parameter of the plurality of parameters for each of the plurality of parameters. A score is determined for each parameter using the created first matrix and the eigenvalue vector. A parameter set is identified based on the determined score for each parameter.

Abstract: A filter auto-calibration system comprises a multi-clock module that includes a multi-clock generator configured to generate a first variable frequency signal based on a channel setting, the multi-clock generator comprising a quadrature signal generator configured to generate an in-phase component and a quadrature component of the first variable frequency signal; and a mixer configured to generate an in-phase component and a quadrature component of a quadrature signal from a received signal other than the first variable frequency signal. The system also comprises at least one filter to be calibrated, and an auto-calibration control module coupled to the multi-clock module and the at least one filter, the auto-calibration control module configured to receive the in-phase component and quadrature component of the first variable frequency signal from the multi-clock module, and configured to control calibration of the at least one filter based on the channel setting.

Abstract: An operation of a system is controlled according to a control trajectory represented by a solution of a set of differential equations satisfying boundary conditions, wherein the set of differential equations includes ordered piecewise differential equations. The set of differential equations is parameterized to produce a first set of parameters representing values of the solution at switching times and a second set of parameters representing values of the switching times. The first and the second sets of parameters are determined alternately until the boundary conditions are satisfied to produce the solution; and the control trajectory is generated based on the solution to control the operation of the system.