Abstract: A method of preparing self-aligned isolation regions between two neighboring sensor elements on a substrate. The method includes patterning an oxide layer to form an opening between the two neighboring sensor elements on the substrate. The method further includes performing a first implant to form a deep doped region between the two neighboring sensor elements and starting at a distance below a top surface of the substrate. The method further includes performing a second implant to form a shallow doped region between the two neighboring sensor elements, wherein a bottom portion of the shallow doped region overlaps with a top portion of the deep doped region.

Abstract: The present invention is directed to a novel synthetic method for producing nanoscale heterostructures, and particularly nanoscale heterostructure particles, rods and sheets, that comprise a metal core and a monocrystalline semiconductor shell with substantial lattice mismatches between them. More specifically, the invention concerns the use of controlled soft acid-base coordination reactions between molecular complexes and colloidal nanostructures to drive the nanoscale monocrystalline growth of the semiconductor shell with a lattice structure incommensurate with that of the core. The invention also relates to more complex hybrid core-shell structures that exhibit azimuthal and radial nano-tailoring of structures. The invention is additionally directed to the use of such compositions in semiconductor devices.

Abstract: The invention provides a method for forming thin film transistors including a polycrystalline semiconducting film. The method comprises depositing a first layer of amorphous semiconducting thin film on to a substrate; depositing a second layer of thin film on to the first layer of amorphous semiconducting thin film; patterning the second layer of thin film so that the first layer of amorphous semiconducting thin film is exposed at selected locations; exposing the first and second layers of thin film to a nickel containing compound in either a solution or a vapor phase ; removing the second layer of thin film; and annealing the first layer of amorphous semiconducting thin film at an elevated temperature so the first layer of amorphous semiconducting thin film converts into a polycrystalline semiconducting thin film.

Abstract: A transistor having a bottom gate formed from a layer of gate material and a channel region formed from a layer semiconductor material. In some examples, the layer of gate material is patterned separately from the layer of semiconductor material. In some examples the patterning of the layer of gate material also leaves other conductive structures that may be, in some examples, used to provide a bottom gate bias voltage to the bottom gate. In some examples, the layer of semiconductor material is formed by bonding two wafers together with a substrate of one of the wafers being cleaved, wherein a remaining portion of the semiconductor substrate is a semiconductor layer from which the channel region is formed.