Patents Examined by Matthew W Wahlin
  • Patent number: 12216535
    Abstract: A request to validate a project object model (POM) is received from a client device. The POM references one or more modules, each of which is associated with one or more artifacts. The artifacts associated with a module are downloaded to a staging repository along with checksums of the artifacts. The downloaded checksum is compared to a checksum calculated on the staging repository. Upon determining that the downloaded checksum matches the calculated checksum for all artifacts of all modules, the POM is moved to the staging repository.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: February 4, 2025
    Assignee: Red Hat, Inc.
    Inventors: Andrea Cosentino, Paolo Antinori
  • Patent number: 12216536
    Abstract: Example embodiments relate to low-overhead, bidirectional error checking for a serial peripheral interface. An example device includes an integrated circuit. The device also includes a serial peripheral interface (SPI) with a Master In Slave Out (MISO) channel and a Master Out Slave In (MOSI) channel. The MOSI channel is configured to receive a write address, payload data, and a forward error-checking code usable to identify data corruption within the write address or the payload data. The integrated circuit is configured to calculate and provide a reverse error-checking code usable to identify data corruption within the write address or the payload data. Additionally, the integrated circuit is configured to compare the forward error-checking code to the reverse error-checking code. Further, the integrated circuit is configured to write, to the write address if the forward error-checking code matches the reverse error-checking code, the payload data.
    Type: Grant
    Filed: November 17, 2023
    Date of Patent: February 4, 2025
    Assignee: Waymo LLC
    Inventors: Kaushik Kannan, David Sobel
  • Patent number: 12204410
    Abstract: A codeword read from memory includes data blocks including data and supplemental blocks including error correction code (ECC) symbols for detecting and correcting data errors. Metadata can be stored in the supplemental blocks to increase memory utilization but using bits of the supplemental blocks for metadata leaves too few bits remaining for the ECC symbols. To maintain error protection, the supplemental blocks include ECC symbols to protect a first data portion of the codeword and parity bits configured to protect a second data portion of the codeword. Errors in the first data portion can be located and corrected using the ECC symbols. Errors in the second data portion can be detected by the parity. For example, the first data portion is encoded based on the second data portion, so locations of parity errors correspond to locations of symbol errors, and parity errors can be corrected.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: January 21, 2025
    Assignee: Ampere Computing LLC
    Inventors: Massimo Sutera, Nagi Aboulenein, Sandeep Brahmadathan
  • Patent number: 12174698
    Abstract: An apparatus for on demand access and cache encoding of repair data. In one embodiment the apparatus includes an integrated circuit having a data cache in data communication with a non-volatile memory, a controller of a built-in self-test-and-repair (BISTR) circuit, and a plurality of registers. The controller is configured to read data from the data cache and store it into a first of the plurality of registers.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: December 24, 2024
    Assignee: Cypress Semiconductor Corporation
    Inventor: Senwen Kan
  • Patent number: 12165720
    Abstract: Systems, apparatuses and methods may provide technology for intelligent drive wear management. The technology may include determining a difference between a wear value derived for a first solid state storage drive and a wear value derived for a second solid state storage drive, and if the difference in wear value exceeds a wear skew threshold, swapping content between the first drive and the second drive. The technology may also include sorting an array of solid state storage drives into a plurality of drive groups based on a wear value derived for each drive, and determining, for a first pair of drives in a drive group, a difference in wear value between the drives in the first pair. Respective pairs of drives in a drive group may be selected based on the drive wear value and a drive rotation counter value associated with each drive.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: December 10, 2024
    Assignee: Intel Corporation
    Inventors: Corey Gough, Nityasrilalitha Gollamudi, Mihir Patel
  • Patent number: 12124328
    Abstract: A memory controller includes a transaction scheduler circuit and a command queue. For each access request received by the memory controller, the transaction scheduler circuit is configured to allocate a new entry in a scheduler queue, store an access address corresponding to the access request as a data address into the new entry, generate an error correction code (ECC) address from the data address and store the ECC address into the new entry, and set a corresponding ECC mode field in the new entry to indicate whether the data address or ECC address of the new entry is to be exposed during arbitration. The transaction scheduler circuit, during an arbitration cycle, is configured to select a transaction from the scheduler queue using an exposed address of each valid entry, and is configured to provide the selected transaction to the command queue.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: October 22, 2024
    Assignee: NXP USA, Inc.
    Inventors: Diviya Jain, James Andrew Welker
  • Patent number: 12119071
    Abstract: Methods, systems, and apparatuses include receiving, from a host, an error check functionality request for a memory device that stores encoded data. The encoded data is written to a verification portion of memory with at least one intentional error. A read command of the verification portion is initiated in response to the request. An error check functionality indicator is determined based on a result of the read command and a number of intentional errors in the encoded data. The error check functionality indicator corresponding to the number intentional errors in the encoded data is sent to the host.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: October 15, 2024
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Francesco Lupo
  • Patent number: 12099903
    Abstract: One or more systems, devices, computer program products and/or computer-implemented methods of use provided herein relate to a process to dynamically determine a threshold for determining a state of a qubit and apply the threshold for operating a pulse to de-excite the qubit. A system can comprise a memory that stores computer executable components, and a processor that executes the computer executable components stored in the memory, wherein the computer executable components can comprise a decision component that is configured to determine a threshold of a plurality of thresholds to apply to measurement of a state of a qubit based on a probability distribution of state of the qubit, wherein a measurement at one side of the threshold is representative of the qubit being in the ground state, and wherein a measurement at another side of the threshold is representative of the qubit being in an excited state.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: September 24, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ken Inoue, Maika Takita, Antonio Corcoles-Gonzalez, Scott Douglas Lekuch
  • Patent number: 12078678
    Abstract: Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.
    Type: Grant
    Filed: July 6, 2023
    Date of Patent: September 3, 2024
    Assignee: NVIDIA Corporation
    Inventors: Shantanu Sarangi, Jae Wu, Andi Skende, Rajith Mavila
  • Patent number: 12081345
    Abstract: A method and an initiator device for autonomous detection of status of a link between the initiator device and a target device in a Universal Flash Storage (UFS) system. The method includes determining whether an Acknowledgement and Flow Control (AFC) frame for a data frame is received before expiry of a turn-around timer. If the AFC frame is received from the target device before expiry of the turn-around timer, then the method detects the status of the link between the initiator device and the target device as active. If the AFC frame is not received from the target device before expiry of the turn-around timer then, the method detects the status of the link between the initiator device and the target device by restarting the turn-around timer with a second time period.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: September 3, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dipakkumar Prafulkumar Abhani, Vasudevan Subramaniam, Ken Joseph Kannampuzha
  • Patent number: 12057859
    Abstract: Techniques for implementing a local neural network and global decoding scheme for quantum error correction of circuit-level noise within quantum surface codes such that the decoding schemes have fast decoding throughout and low latency times for quantum algorithms are disclosed. A local neural network decoder may be pre-trained via a supervised learning technique such that the local neural network decoder may be applied for error correction in the presence of circuit-level noise in arbitrarily sized surface codes in a local decoding stage. Prior to a global decoding stage, an intermediate stage may be used to remove vertical pairs of highlighted vertices within the matching graph, which may reduce a syndrome density within the matching graph to allow for faster decoding at the global decoding stage. Such an intermediate stage may include application of a syndrome collapse or vertical cleanup technique.
    Type: Grant
    Filed: September 30, 2022
    Date of Patent: August 6, 2024
    Assignee: Amazon Technologies, Inc.
    Inventors: Christopher Chamberland, Luis Goncalves, Prasahnt Sivarajah, Eric Christopher Peterson, Sebastian Johannes Grimberg
  • Patent number: 12046295
    Abstract: The present technology includes a method of operating a controller capable of controlling a semiconductor memory device including a plurality of memory cells. The method of operating the controller includes sensing error correction failure of data read from the semiconductor memory device, generating a new read voltage for re-reading the data, determining whether the new read voltage belongs to an allowable range depending on a read voltage statistical value of previous read voltages according to which error corrections were successful on previously read data, and determining, based on a result of the determining whether the new read voltage belongs to the allowable range, a read voltage to be used in a next read operation of re-reading the data.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: July 23, 2024
    Assignee: SK hynix Inc.
    Inventor: Sang Ho Yun
  • Patent number: 12045128
    Abstract: The technology disclosed herein includes a memory to store a plurality of pages, a page of the plurality of pages configured as one of a trusted execution environment (TEE) configuration and a non-TEE configuration, and a memory controller to attempt to access the page using a memory address and the TEE configuration and generate a first error correcting code (ECC); and when data for the first ECC is at least one of correct and correctable by ECC for the attempt to access the page using the TEE configuration, attempt to access the page using the memory address and the non-TEE configuration and generate a second ECC, and when data the second ECC is at least one of correct and correctable by ECC for the attempt to access the page using the non-TEE configuration, store the memory address as an unknown cacheline address.
    Type: Grant
    Filed: December 28, 2022
    Date of Patent: July 23, 2024
    Assignee: Intel Corporation
    Inventors: David M. Durham, Sergej Deutsch, Karanvir Grewal
  • Patent number: 12033710
    Abstract: Performing a built-in self-test (BIST) on a memory macro includes generating a plurality of input vectors. One input vector is transmitted to the memory macro in each of a plurality of cycles. Each of the plurality of input vectors is associated with a bit width. Generating the input vector includes generating a partial input vector of half the bit width and transmitting the partial input vector to each of a first half of the memory macro and a second half of the memory macro. The method also includes receiving, in each of the plurality of cycles, an output data from the memory macro, such that the output data is generated by the memory macro in response to processing the partial input vector, comparing the output data with a signature value, and determining whether the memory macro is normal or faulty based upon the comparison.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: July 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ted Wong, Saman Adham, Marat Gershoig
  • Patent number: 11984179
    Abstract: A redundant circuit assigning method includes: executing a first test item to obtain first test data including position data of fail bits acquired during execution of the first test item; determining a first redundant circuit assigning result according to the first test data, where the first redundant circuit assigning result includes a number of assigned local redundant circuits and their corresponding position data; executing a second test item to obtain second test data including position data of fail bits acquired during execution of the second test item; and determining a second redundant circuit assigning result according to the first test data and the second test data, when the fail bits acquired during the execution of the second test item include one or more fail bits beyond a repair range of the assigned local redundant circuits and assigned global redundant circuits and when assignable local redundant circuits have been assigned.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: May 14, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yui-Lang Chen
  • Patent number: 11908527
    Abstract: The present technology relates to an electronic device. According to the present technology, a memory device may include memory cells respectively connected to a plurality of word lines, a peripheral circuit configured to perform a read operation of reading data stored in selected memory cells connected to a selected word line among the memory cells, and a read operation controller configured to control the peripheral circuit to apply a pass voltage to adjacent word lines adjacent to the selected word line during the read operation, discharge the pass voltage to a target pass voltage less than the pass voltage after a predetermined time elapses, and obtain data stored in the selected memory cells through bit lines connected to the selected memory cells after a target read time elapses, after a voltage applied to the adjacent word lines is discharged to the target pass voltage.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: February 20, 2024
    Assignee: SK hynix Inc.
    Inventors: Dong Jae Jung, Sung Won Bae
  • Patent number: 11894084
    Abstract: Method, systems and apparatuses may provide for technology that executes a margin test of a first memory storage based on a subset of first signals associated with the first memory storage. The technology determines, based on the margin test, first margin data to indicate whether the first memory storage complies with one or more electrical constraints. The technology determines, based on the first margin data, whether to execute a signal training process.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: February 6, 2024
    Assignee: Intel Corporation
    Inventors: Dujian Wu, Shijian Ge, Daocheng Bu
  • Patent number: 11881278
    Abstract: A redundant circuit assigning method a includes: first test item is executed and first test data is acquired; a first redundant circuit assigning result including the number of assigned local redundant circuits and position data of the assigned local redundant circuits is determined according to the first test data; a second test item is executed and second test data is acquired; when fail bits acquired during execution of the second test item include one or more fail bits beyond the repair range of the assigned local redundant circuits and assigned global redundant circuits, and the assignable redundant circuits have been assigned out, target position data of fail bits in a target subdomain and a related subdomain is acquired based on the first test data and the second test data; and a second redundant circuit assigning result is determined according to the first test data and the second test data.
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: January 23, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yui-Lang Chen
  • Patent number: 11860229
    Abstract: An automated test equipment (ATE) apparatus comprising a tester processor operable to generate commands and data for coordinating testing of a plurality of devices under test (DUTs). The ATE further comprises a field programmable gate array (FPGA) communicatively coupled to the tester processor, wherein the FPGA comprises routing logic operable to route signals associated with the commands and data in the FPGA based on a type of the device under test (DUT). Further, the ATE comprises a connector module communicatively coupled to the FPGA comprising a socket to which the DUT connects and further comprising circuitry for routing the signals to a set of pins on the DUT, wherein the set of pins are associated with a first type of DUT. The circuitry can support multiple different DUT types having a common form factor but different pinout assignments.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: January 2, 2024
    Assignee: Advantest Corporation
    Inventor: Mei-Mei Su
  • Patent number: 11862269
    Abstract: A testing method for a packaged chip includes: acquiring a target chip; in the post-burn-in test process, testing a first data retention time of each memory unit on the target chip; comparing the first data retention time of each memory unit with a preset reference time; and, determining that the target chip is a qualified chip if the first data retention time of each memory unit is not less than the preset reference time. In the present application, by testing the first data retention time of each memory unit on the target chip in the post-burn-in test process, it is determined that the target chip is a qualified chip if the first data retention time of each memory unit is not less than the preset reference time.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Cheng-Jer Yang