Abstract: A memory device such as a page mode NAND flash including a page buffer, and an input/output interface for I/O data units having an I/O width less than the page width supports continuous page read with non-sequential addresses. A controller controls a continuous page read operation to output a stream of pages at the I/O interface. The continuous read operation includes responding to a series of commands to output a continuous stream of pages. The series of commands including a first command and a plurality of intra-stream commands received before completing output of a preceding page in the stream. The first command includes an address to initiate the continuous page read operation, and at least one intra-stream command in the plurality of intra-stream commands includes a non-sequential address to provide the non-sequential page in the stream of pages.

Abstract: A circuit apparatus 100 includes: an interface circuit 120 that receives setting data; and a control circuit 110 that controls the operations of the circuit apparatus 100 based on the setting data and also controls access to a nonvolatile memory 10. The control circuit 110 generates error detection data based on the setting data received by the interface circuit 120, and writes the setting data and the error detection data to the nonvolatile memory 10.

Abstract: Scan-chain testing of a semiconductor chip may be performed entirely via a deserializer port. In one illustrative device embodiment, a semiconductor chip includes at least one deserializer having: a serial-to-parallel converter coupled to a pair of differential signal input pins; a scan-chain receiver circuit coupled to at least one of the pair of differential signal input pins in parallel with the serial-to-parallel converter to receive a scan-chain test input data stream; a scan-chain test logic circuit that loads the scan-chain test input data stream into a scan chain and extracts a scan-chain test result data stream from the scan chain; and a scan-chain transmit circuit that drives the pair of differential signal input pins with the scan-chain test result data stream. If multiple SerDes blocks exist on the chip, the deserializer ports may be employed in parallel for input and output of test data streams.

Abstract: A base matrix is applied to an LDPC coder. The base matrix includes multiple parts, each including multiple of rows and columns, and containing integers, each representative of an identity matrix cyclically shifted in accordance with the integer or representative of an all-zero matrix. At least two of the multiple parts are configured such that their respective column-wise combinations of rows represents a same starting vector, cyclically shifted or interleaved, with zero or more but not all integers not indicative of the all-zero matrix of the same vector substituted by integers indicative of the all-zero matrix. The at least two of the multiple parts are not identical. The applied base matrix is used for one of encoding data using the LDPC coder or decoding data using the LDPC coder.

Abstract: A memory device such as a page mode NAND flash is operated, using a first pipeline stage, to clear a page buffer to a second buffer level, and transfer a page to the page buffer; a second pipeline stage to clear the second buffer level to the third buffer level and transfer the page from the page buffer to the second buffer level; a third pipeline stage to move the page to the third buffer level and execute in an interleaved fashion a first ECC function over data in a first part of the page and output the first part of the page while performing an second ECC function, and to execute the first ECC function over data in a second part of the page in the third buffer level, and to output the second part while performing the second ECC function.

Abstract: A communication scheme and system for converging a 5th generation (5G) communication system for supporting a data rate higher than that of a 4th generation (4G) system with an internet of things (IoT) technology are provided. The present disclosure is applicable to intelligent services (e.g., smart home, smart building, smart city, smart car or connected car, health care, digital education, retail, and security and safety-related services) based on the 5G communication technology and the IoT-related technology. The disclosure relates to a punctured polar code design method and apparatus and proposes optimal puncturing pattern and information set selection criteria for designing punctured polar codes.

Abstract: A memory system comprises: a memory cell array suitable for storing first data and a first parity, which is used to correct an error of the first data; and an error correcting circuit suitable for generating second data and a second parity, which includes bits obtained by correcting an error of the first parity and a bit obtained by correcting an error of a second sub-parity; wherein the error correcting circuit includes: a single error correction and double error detection (SECDED) parity generator suitable for generating a second pre-parity, which includes a first sub-parity and the second sub-parity; a syndrome decoder suitable for generating a first parity error flag and a first data error flag by decoding a syndrome; a SEC parity corrector suitable for correcting an error of the first parity based on the first parity error flag; a DED parity error detector suitable for generating a second sub-parity error flag based on an error information of the first data used to generate the second sub-parity; and a D

Abstract: A method for performing error recovery for data stored on a track of a storage device, in which the method includes: receiving a request to read the data from the storage device, identifying a plurality of sectors of the track to be read in response to the request, reading the data from the plurality of sectors of the track and parity data, based on the data read from the plurality of sectors, determining whether any of the plurality of sectors corresponds to a failed sector, and recovering a portion of the data from the failed sector using the parity data and portions of the data stored in remaining ones of the plurality of sectors.

Abstract: Embodiments may relate to a processor to an electronic device that includes an error correction code (ECC) encoder that is to perform ECC encoding on aa data message to generate an ECC encoded data message. The electronic device may further include a data bus inversion (DBI) encoder communicatively coupled with the ECC encoder, wherein the DBI encoder is to perform DBI encoding on the ECC encoded data message to generate a DBI encoded data message. Other embodiments may be described or claimed.

Abstract: Memory with an error correction circuit includes: a first error correction circuit performing error correction on first partial data to generate first partial write data or first partial read data; and a second error correction circuit performing error correction on second partial data to generate second partial write data or second partial read data. In a write mode, a plurality of sensing drive circuits respectively receive a plurality of first partial write bits of the first partial write data and a plurality of second partial write bits of the second partial write data, and each sensing drive circuit combines the first partial write bits with the corresponding second partial write bits and writes them to corresponding memory cell columns; in a read mode, the sensing driving circuits respectively sense stored data in the memory cell columns to generate a plurality of first partial read data and second partial read data.

Abstract: Examples herein describe a self-test process where an integrated circuit includes a test controller responsible for testing a plurality of frames in the memory of an integrated circuit. The test controller can receive a test pattern which the controller duplicates and stores in each of the plurality of frames. However, frames may be non-uniform meaning the frames have varying sizes. As such, some of the frames may only store parts of the test pattern rather than all of it. In any case, the test controller reads out the stored data and generates a checksum which can then be compared to a baseline checksum generated from simulating the integrated circuit using design code to determine whether there is a manufacturing defect in the frames.

Abstract: A system for debugging circuits includes an integrated circuit configured to implement a circuit under test and a logic analyzer controller coupled to the circuit under test. The system includes a host computing system configured to communicate with the logic analyzer controller and provide a debug command to the logic analyzer controller. The logic analyzer controller, in response to the debug command, controls operation of the circuit under test.

Abstract: Examples described herein can be used to reduce a number of re-read operations and potentially avoid data recovery operations, which can be time consuming. A determination can be made of a read voltage to apply during an operation to cause a read of data stored in a region of a memory device. The region of the memory device can be read using the read voltage. If the region is not successfully read, then an error level indication can be measured and a second read voltage can be determined for a re-read operation. If the re-read operation is not successful, then a second error level indication can be measured for the re-read operation. A third read voltage can be selected based on the change from the error level indication to the second error level indication.

Abstract: Apparatuses and methods generally relating to a sort system, such as may be used in a data processing kernel, for list decoding of a Polar codeword are described. In one such sort system, a sorter circuit is configured to receive and sort path metrics for coded bits of the Polar codeword. The path metrics are obtained from log-likelihood ratios associated with the coded bits. A limiter circuit is configured to cull the sorted path metrics to provide a list having a subset of the path metrics to limit output paths of a list decoder. A normalizer circuit is configured to subtract a path metric of the path metrics or a threshold metric representing a minimum metric respectively from entries in the list to provide normalized path metrics to decode the Polar codeword.