Abstract: A reduced permittivity interlevel dielectric in a semiconductor device arranged between two levels of interconnect. The dielectric comprises a first dielectric layer preferably from a silane source deposited on a first level interconnect to form air gaps at midpoints between adjacent first interconnect structures, a second dielectric containing air gap trenches at spaced intervals across the second dielectric, and a third dielectric formed upon said second dielectric. A second interconnect level is formed on the third dielectric.

Abstract: An Si.sub.3 N.sub.4 layer is formed on a surface of a wafer, which is an object to be processed, at a high temperature of, for example, 780.degree. C., using a vertical thermal processing apparatus having a reaction tube of a double-wall structure comprising an inner tube and an outer tube in which a predetermined reduced-pressure status is maintained within the reaction tube while a reaction gas comprising, for example, SiH.sub.2 Cl.sub.2 and NH.sub.3 is made to flow from an inner side to an outer side of the inner tube by the action of a first gas supply pipe and first exhaust pipe provided in the thermal processing apparatus. Next, the temperature in the interior of the reaction tube is raised to, for example, 1000.degree. C., a reaction gas comprising, for example, H.sub.2 O vapor and HCl is made to flow from the outer side to the inner side of the inner tube by the action of a second gas supply pipe and second exhaust pipe, and an SiO.sub.2 layer is formed by the oxidation of the surface of the Si.sub.