Abstract: To achieve TFT having a high light-resistance characteristic with a suppressed light leak current at low cost by simplifying the manufacturing processes. The TFT basically includes a light-shielding film formed on a glass substrate that serves as an insulating substrate; an insulating film formed on the light-shielding film; a semiconductor film formed on the insulating film; and a gate insulating film formed on the semiconductor film. Each layer of a laminate that is configured with three layers of the light-shielding film, the insulating film, and the semiconductor film is patterned simultaneously. Further, each layer of the laminate is configured with silicon or a material containing silicon.

Abstract: Disclosed are methods of making and using a high-K dielectric liner to facilitate the lateral oxidation of a high-K gate dielectric, integrated circuit structures containing the high-K dielectric liner and/or oxidized high-K gate dielectric, and other associated methods.

Abstract: An LED assembly is provided herein. The assembly comprises a thermally conductive housing (201), wherein a portion of said housing is equipped with a plurality of fins (203); an LED (205) disposed in said housing; and a synthetic jet actuator (207) adapted to direct a synthetic jet onto said portion of the housing.

Abstract: A method of fabricating an OLED display, includes sequentially forming a TFT array, first electrodes, and a first related layer on a first substrate, respectively forming heat-generating elements on second and third substrates, forming a red organic emission pattern on the second substrate, and forming a green organic emission pattern on the third substrate, aligning and attaching the first and second substrates, applying a voltage to heat-generating elements to transfer the red organic emission pattern to red pixel regions, thereby forming red organic emission layers, aligning and attaching the first and third substrates, applying a voltage to the heat-generating elements to transfer the green organic emission pattern to green pixel regions, thereby forming green organic emission layers, entirely depositing a blue organic emission material on the first substrate, thereby forming a blue organic emission layer, and sequentially forming a second related layer and a second electrode on the first substrate.

Abstract: The present invention relates to flash memory devices and a method of fabricating the same. In an aspect of the present invention, the flash memory device includes trenches formed in a semiconductor substrate and having a step at their lower portion, a tunnel insulating layer formed in an active region of the semiconductor substrate, first conductive layers formed on the tunnel insulating layer, an isolation layer gap-filling between the trenches and the first conductive layers, and a second conductive layer formed on the first conductive layer and having one side partially overlapping with the isolation layers.

Abstract: This invention provides a means for suppressing streaks of light emission in an organic EL display having an organic light-emitting layer formed by coating by an ink jet method. A manufacturing process of the organic EL display of this invention includes: preparing a display substrate having two or more linear banks in parallel to each other, and two or more pixel regions arranged in a region between the linear banks; arranging an ink jet head such that the alignment direction of nozzles and the line direction of the linear banks are in parallel; and relatively moving the ink jet head in a direction perpendicular to the line direction of the linear banks and discharging the ink from the nozzles to apply the ink to every region defined by the linear banks.

Abstract: A method of forming multiple conductive structures in a semiconductor device includes forming spacers adjacent side surfaces of a mask, where the mask and the spacers are formed on a conductive layer. The method also includes etching at least one trench in a portion of the conductive layer not covered by the spacers or the mask. The method may further include depositing a material over the semiconductor device, removing the mask and etching the conductive layer to remove portions of the conductive layer not covered by the spacers or the material, where remaining portions of the conductive layer form the conductive structures.

Abstract: One aspect of the present invention relates to a method for fabricating a polycrystalline silicon film. In one embodiment, the method includes the steps of providing a substrate having a thermally-grown silicon dioxide layer, forming an amorphous silicon film on the thermally-grown silicon dioxide layer of the substrate, forming an aluminum layer on the amorphous silicon film to form a structure having the substrate, the amorphous silicon film and the aluminum layer, and annealing the structure at an annealing temperature for a period of time in an N2 environment with a ramp-up time to crystallize the amorphous silicon film to form a polycrystalline silicon film.

Abstract: Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of the at least one conductive trace. At least one interconnect structure extends through a portion of the at least one conductive trace and a portion of the insulative material, the at least one interconnect structure comprising a transverse cross-sectional dimension through the at least one conductive trace which differs from a transverse cross-sectional dimension through the insulative material. Methods of forming semiconductor devices comprising at least one interconnect structure are also disclosed.

Abstract: A method for fabricating a partial silicon-on-insulator (SOI) substrate is disclosed. The method for fabricating a partial silicon-on-insulator (SOI) substrate includes forming an insulation pattern over a first silicon layer, forming a second silicon layer over the substrate structure including the insulation pattern, etching the second silicon layer to form trenches, and forming device isolation regions filling the trenches.

Abstract: A method for manufacturing a semiconductor device includes: mounting a wafer having an exposed silicon nitride film, on an electrode received in a plasma chamber; dry-cleaning the chamber to remove reaction products accumulated on the wall and ceiling of the chamber, anisotropic-etching the silicon nitride film and an underlying silicon film for patterning; and removing the wafer from the chamber. The method repeats the treatment for a number of semiconductor wafers.

Abstract: A method for manufacturing a metal-semiconductor contact in semiconductor Components is disclosed. There is a relatively high risk of contamination in the course of metal depositions in prior-art methods. In the disclosed method, the actual metal -semiconductor or Schottky contact is produced only after the application of a protective layer system, as a result of which it is possible to use any metals, particularly platinum, without the risk of contamination.

Abstract: A method for fabricating a semiconductor with a fuse includes providing a substrate, forming an insulation layer over the substrate, forming a polysilicon hard mask over the insulation layer, forming a first mask pattern to form a fuse over the polysilicon hard mask, and removing the polysilicon hard mask exposed by the first mask pattern to form a portion of the polysilicon hard mask into a polysilicon fuse.

Abstract: A ball grid array type board on chip package may include an integrated circuit chip having an active surface that supports a plurality of contact pads. An interposer may be adhered to the active surface of the integrated circuit chip. At least one hole may be provided through the interposer to expose the contact pads. A board, which may have a first surface supporting a plurality of metal lines, may have a second surface adhered to the interposer. The board may have an opening through which the contact pads may be exposed. A plurality of bonding wires may connect the contact pads to the metal lines through the opening.

Abstract: A semiconductor device is made by forming a photoresist layer over a metal carrier. A plurality of openings is formed in the photoresist layer extending to the metal carrier. A conductive material is selectively plated in the openings of the photoresist layer using the metal carrier as an electroplating current path to form wettable contact pads. A semiconductor die has bumps formed on its surface. The bumps are directly mounted to the wettable contact pads to align the die with respect to the wettable contact pads. An encapsulant is deposited over the die. The metal carrier is removed. An interconnect structure is formed over the encapsulant and electrically connected to the wettable contact pads. A plurality of conductive vias is formed through the encapsulant and extends to the contact pads. The conductive vias are aligned by the wettable contact pads with respect to the die to reduce interconnect pitch.

Abstract: Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the main portions of the trenches and field oxide regions may be used to protect the structures from erosion during later process steps. The top surfaces of the isolation structures are coplanar with the surface of the substrate. Field doping regions may be formed beneath the field oxide regions. To meet the demands of different devices, the isolation structures may have varying widths and depths.

Abstract: We have used the state-of-the-art computational chemistry techniques to identify adhesion promoting layer materials that provide good adhesion of copper seed layer to the adhesion promoting layer and the adhesion promoting layer to the barrier layer. We have identified factors responsible for providing good adhesion of copper layer on various metallic surfaces and circumstances under which agglomeration of copper film occur. Several promising adhesion promoting layer materials based on chromium alloys have been predicted to be able to significantly enhance the adhesion of copper films. Chromium containing complexes of a polydentate ?-ketoiminate have been identified as chromium containing precursors to make the alloys with chromium.

Abstract: A semiconductor device includes a first insulating layer, a capacitor, an adhesive layer, and an intermediate layer. The first insulating layer may include a first insulating film. The first insulating layered structure has a first hole. The capacitor is disposed in the first hole. The capacitor may include bottom and top electrodes and a capacitive insulating film. The capacitive insulating film is sandwiched between the bottom and top electrodes. The adhesive layer contacts with the bottom electrode. The adhesive layer has adhesiveness to the bottom electrode. The intermediate layer is interposed between the adhesive layer and the first insulating film. The intermediate layer contacts with the adhesive layer and with the first insulating film. The intermediate layer has adhesiveness to the adhesive layer and to the first insulating film.

Abstract: Embodiments relate to a flash memory device and a method of manufacturing a flash memory device, which may increase a coupling coefficient between a control gate and a floating gate by increasing a surface area of floating gate. In embodiments, a flash memory device may be formed by forming a photoresist pattern for forming a floating gate on a semiconductor substrate including an oxide film, a floating gate poly film, and a BARC (Bottom AntiReflect Coating), performing a first etching process using the photoresist pattern as a mask, to etch the floating gate poly film to a predetermined depth, depositing and forming a polymer to cover the photoresist pattern, forming spacers of the polymer at both sidewalls of the photoresist pattern, forming a second etching process using the spacers as a mask, to expose the oxide film, and removing the BARC, the photoresist pattern and the spacers by ashing and stripping.

Abstract: This invention is directed to offer a technology that makes it possible to form desired bump electrodes easily when the bump electrodes are to be formed at locations lowered by a step. There is formed an isolation layer 12 to isolate each of bump electrode forming regions 11. The isolation layer 12 is a resist layer, for example, and is formed by exposure and development processes, for example. Each of the bump electrode forming regions 11 is surrounded by the isolation layer 12 and a protection layer 10 that covers a side surface of a semiconductor substrate 2. Then, a printing mask 16 that has openings 15 at locations corresponding to the bump electrode forming regions 11 is placed above the semiconductor substrate 2. Next, solder 17 in paste form is applied to the printing mask 16. Then the solder 17 is applied to a metal layer 9 by moving a squeeze 18 at a constant speed. Bump electrodes 19 are obtained by heating, melting and re-crystallizing the solder 17 after removing the printing mask 16.