Abstract: An LED assembly is provided herein. The assembly comprises a thermally conductive housing (201), wherein a portion of said housing is equipped with a plurality of fins (203); an LED (205) disposed in said housing; and a synthetic jet actuator (207) adapted to direct a synthetic jet onto said portion of the housing.

Abstract: There are provided the steps of connecting a chip component 13 to a first substrate 10 through wire bonding, providing, on a second substrate 20, an electrode 21 having a solder coat 23 with a copper core 22, polishing a portion of the electrode 21 which is to be bonded to the connecting pad 12, thereby exposing the copper core 22 from the solder coat 23, bonding the exposed portion of the copper core 22 to the bump connecting pad 12 by using a flux non-containing conductive paste 30, thereby bonding the substrates 10 and 20 to each other, and filling a sealing resin 40 in a clearance portion between the substrates 10 and 20.

Abstract: This invention pertains to methods and systems for fabricating semiconductor devices. One aspect of the present invention is a method of depositing a gapfill copper layer onto barrier layer for semiconductor device metallization. In one embodiment, the method includes forming the barrier layer on a surface of a substrate and subjecting the barrier layer to a process condition so as to form a removable passivated surface on the barrier layer. The method further includes removing the passivated surface from the barrier layer and depositing the gapfill copper layer onto the barrier layer. Another aspect of the present invention is an integrated system for depositing a copper layer onto a barrier layer for semiconductor device metallization.

Abstract: An alignment key structure in a semiconductor device is provided. The alignment key structure includes an insulation layer formed on a substrate, and a passivation layer pattern formed on the insulation layer. The insulation layer includes a plurality of metal wirings. The passivation layer pattern includes a first opening that exposes at least one of the metal wirings. Moreover, the first opening has a width which is narrower than a width of the exposed metal wiring.

Abstract: A silicon structure with improved protection against failures induced by excess radiation-induced charge carrier migration from the bulk region into the near-surface region. The structure comprises bulk and near-surface regions that are doped with a dopant, wherein the concentration in the near-surface region is at least 10 times the maximum concentration, c, of dopant in the bulk region. The structure further comprises a transition region between the bulk and near-surface regions extending less than about 1 ?m from the near-surface region toward the central plane.

Abstract: A method and system for providing a twin well in a semiconductor device is described. The method and system include providing at least one interference layer and providing a first mask that covers a first portion of the semiconductor device and uncovers a second portion of the semiconductor device. The first and second portions of the semiconductor device are adjacent. The method and system also include implanting a first well in the second portion of the semiconductor device after the first mask is provided. The method and system also include providing a second mask. The interference layer(s) are configured such that energy during a blanket exposure develops the second mask that uncovers the first portion and covers the second portion of the semiconductor device. The method and system also include implanting a second well in the first portion of the semiconductor device after the second mask is provided.

Abstract: A method of forming an air gap or gaps within solid structures and specifically semiconductor structures to reduce capacitive coupling between electrical elements such as metal lines, wherein a norbornene-type polymer is used as a sacrificial material to occupy a closed interior volume in a semiconductor structure. The sacrificial material is caused to decompose into one or more gaseous decomposition products which are removed, preferably by diffusion, through an overcoat layer. The decomposition of the sacrificial material leaves an air gap or gaps at the closed interior volume previously occupied by the norbornene-type polymer. The air gaps may be disposed between electrical leads to minimize capacitive coupling therebetween.

Abstract: A method for fabricating a semiconductor device with a step gated asymmetric recess is provided.

Abstract: A trench gate type IGBT includes: a first semiconductor layer; a second semiconductor on the first semiconductor layer; a third semiconductor on the second semiconductor layer; trenches for separating the third semiconductor layer into first regions and second regions; a gate insulation film on an inner wall of each trench; a gate electrode on the gate insulation film; a fourth semiconductor layer in a surface portion of each first region and contacting each trench; a first electrode connecting to the first region and the fourth semiconductor layer; and a second electrode connecting to the first semiconductor layer. The first regions and the second regions are alternately arranged. Two second regions are continuously connected together to be integrated into one body.

Abstract: A semiconductor structure including a highly strained selective epitaxial top layer suitable for use in fabricating a strained channel transistor. The top layer is deposited on the uppermost of a series of one or more lower layers. The lattice of each layer is mismatched with the lattice of its subjacent layer by an amount not less than the lattice mismatch between the lowest layer of the series and a substrate on which it resides. A trench is formed in the uppermost series layer. The trench has rounded corners so that a dielectric material filling the trench conforms to the round corners. The rounded corners are produced by heating the uppermost series layer after trench formation.

Abstract: A method of fabricating a thyristor-based memory may include forming different opposite conductivity-type regions in silicon for defining a thyristor and an access device in series relationship. An activation anneal may activate dopants previously implanted for the different regions. A damaging implant of germanium or xenon or argon may be directed into select regions of the silicon including at least one p-n junction region for the access device and the thyristor. A re-crystallization anneal may then be performed to re-crystallize at least some of the damaged lattice structure resulting from the damaging implant. The re-crystallization anneal may use a temperature less than that of the previous activation anneal.

Abstract: The idea of the invention is to coat the free surface of patterned Cu conducting lines in on-chip interconnections (BEOL) wiring by a 1-20 nm thick metal layer prior to deposition of the interlevel dielectric. This coating is sufficiently thin so as to obviate the need for additional planarization by polishing, while providing protection against oxidation and surface, or interface, diffusion of Cu which has been identified by the inventors as the leading contributor to metal line failure by electromigration and thermal stress voiding. Also, the metal layer increases the adhesion strength between the Cu and dielectric so as to further increase lifetime and facilitate process yield. The free surface is a direct result of the CMP (chemical mechanical polishing) in a damascene process or in a dry etching process by which Cu wiring is patterned. It is proposed that the metal capping layer be deposited by a selective process onto the Cu to minimize further processing.

Abstract: An object of the present invention is to provide a method for manufacturing a semiconductor device with high reliability, at low cost, in which an element forming layer having a thin film transistor and the like provided over a substrate is peeled from the substrate, so that a semiconductor device is manufactured. According to the invention, a metal film is formed over a substrate, a plasma treatment is performed to the metal film in a dinitrogen monoxide atmosphere to form a metal oxide film over the metal film, a first insulating film is formed continuously without being exposed to the air, an element forming layer is formed over the first insulating film, and the element forming layer is peeled from the substrate, so that a semiconductor device is manufactured.

Abstract: Semiconductor devices with transistors having different gate dielectric materials and methods of manufacture thereof are disclosed. One embodiment includes a semiconductor device including a workpiece, the workpiece including a first region and a second region proximate the first region. A first transistor is disposed in the first region of the workpiece, the first transistor having at least two first gate electrodes. A first gate dielectric is disposed proximate each of the at least two first gate electrodes, the first gate dielectric comprising a first material. A second transistor is disposed in the second region of the workpiece, the second transistor having at least two second gate electrodes. A second gate dielectric is disposed proximate each of the at least two second gate electrodes, the second gate dielectric comprising a second material. The second material is different than the first material.

Abstract: A method of forming a floating gate of a non-volatile memory device can include etching a mask pattern formed between field isolation regions in a field isolation pattern on a substrate to recess a surface of the mask pattern below an upper surface of adjacent field isolation regions to form an opening having a width defined by a side wall of the adjacent field isolation regions above the surface. Then the adjacent field isolation regions is etched to increase the width of the opening.

Abstract: Fabrication of electronic devices in the “metal layers” of semiconductor devices. Each metal layer includes a dielectric layer that supports a conductive layer, which includes electrically conductive pathways and electronic devices. The metal layers are stacked on top of each other such that the dielectric layers separate the adjacent conductive layers. The electronic devices may be passive devices such as resistors. The resistors are formed by depositing metal onto the dielectric layer and then implanting the metal with oxygen. The conductive layer may be formed of materials such as copper and aluminum.

Abstract: A chip level package utilizing a CGA is described. A semiconductor chip with pillars is molded in an encapsulant. Solder balls are added and connected to the chip pillars. The final package does not require a first level substrate or interposer and is able to be assembled to the next level as is. An additional embodiment describes the addition of a thermal heat sink to the packaged chip.

Abstract: In a method for manufacturing a semiconductor device, either a nickel layer or a nickel-based metal layer is formed on a semiconductor substrate by using a plating process. Then, either the nickel layer or the nickel-based metal layer is washed with one of an aqueous hydrochloric acid solution and an aqueous sulfuric acid solution.

Abstract: In a method for forming a wiring of a semiconductor device using an atomic layer deposition, an insulating interlayer is formed on a substrate. Tantalum amine derivatives represented by a chemical formula Ta(NR1)(NR2R3)3 in which R1, R2 and R3 represent H or C1-C6 alkyl group are introduced onto the insulating interlayer. A portion of the tantalum amine derivatives is chemisorbed on the insulating interlayer. The rest of tantalum amine derivatives non-chemisorbed on the insulating interlayer is removed from the insulating interlayer. A reacting gas is introduced onto the insulating interlayer. A ligand in the tantalum amine derivatives chemisorbed on the insulating interlayer is removed from the tantalum amine derivatives by a chemical reaction between the reacting gas and the ligand to form a solid material including tantalum nitride. The solid material is accumulated on the insulating interlayer through repeating the above processes to form a wiring.

Abstract: A semiconductor device includes: a semiconductor substrate formed with an active region and an isolation region and having a trench formed in the isolation region; an isolation insulating film embedded in the trench of the semiconductor substrate; and semiconductor nanocrystals buried in the isolation insulating film. The coefficient of linear expansion of the semiconductor nanocrystal is closer to that of the semiconductor substrate rather than that of the isolation insulating film, so that stress applied to the active region after a thermal treatment or the like is reduced.