Patents Examined by Meiya Li
  • Patent number: 10411080
    Abstract: A flexible organic electroluminescent device and a method for fabricating the same includes a substrate defined with a display area including a plurality of pixel regions and a non-display area at the outside thereof; a switching thin film transistor and a drive thin film transistor formed at the each pixel region on the substrate; an organic insulating layer deposited on the substrate including the switching thin film transistor and drive thin film transistor to expose a drain electrode of the drive thin film transistor; a first electrode formed in each pixel region on the inorganic insulating layer, and connected to the drain electrode of the drive thin film transistor; banks formed around each pixel region on the substrate including the first electrode and separated from one another; an organic light emitting layer separately formed for each pixel region on the first electrode; a second electrode formed on an entire surface of the display area on the organic light emitting layer; and an organic layer forme
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: September 10, 2019
    Assignee: LG DISPLAY CO., LTD.
    Inventors: SangMoo Song, JiNo Lee, JungChul Kim, DoHyung Kim, SeHwan Na, Taro Hasumi
  • Patent number: 10411019
    Abstract: A device is disclosed that includes a memory bit cell, a first word line, a pair of metal islands and a pair of connection metal lines. The first word line is disposed in a first metal layer and is electrically coupled to the memory bit cell. The pair of metal islands are disposed in the first metal layer at opposite sides of the word line and are electrically coupled to a power supply. The pair of connection metal lines are disposed in a second metal layer and are configured to electrically couple the metal islands to the memory bit cell respectively.
    Type: Grant
    Filed: June 18, 2016
    Date of Patent: September 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hidehiro Fujiwara, Wei-Min Chan, Chih-Yu Lin, Yen-Huei Chen, Hung-Jen Liao
  • Patent number: 10396012
    Abstract: A method providing a high aspect ratio through substrate via in a substrate is described. The through substrate via has vertical sidewalls and a horizontal bottom. The substrate has a horizontal field area surrounding the through substrate via. A first metallic barrier layer is deposited on the sidewalls of the through substrate via. A nitridation process converts a surface portion of the metallic barrier layer to a nitride surface layer. The nitride surface layer enhances the nucleation of subsequent depositions. A first metal layer is deposited to fill the through substrate via. A selective etch creates a recess in the first metal layer in the through substrate via. A second barrier layer is deposited over the recess. A second metal layer is patterned over the second barrier layer filling the recess and creating a contact. Another aspect of the invention is a device produced by the method.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Daniel C Edelstein, Chih-Chao Yang
  • Patent number: 10396013
    Abstract: An advanced through silicon via structure for is described. The device includes a substrate including integrated circuit devices. A high aspect ratio through substrate via is disposed in the substrate. The through substrate via has vertical sidewalls and a horizontal bottom. The substrate has a horizontal field area surrounding the through substrate via. A metallic barrier layer is disposed on the sidewalls of the through substrate via. A surface portion of the metallic barrier layer has been converted to a nitride surface layer by a nitridation process. The nitride surface layer enhances the nucleation of subsequent depositions. A first metal layer fills the through substrate via and has a recess in an upper portion. A second barrier layer is disposed over the recess. A second metal layer is disposed over the second barrier layer and creates a contact.
    Type: Grant
    Filed: October 9, 2016
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Daniel C Edelstein, Chih-Chao Yang
  • Patent number: 10396202
    Abstract: A semiconductor structure includes a plurality of stacked and suspended semiconductor nanosheets located above a semiconductor substrate. Each semiconductor nanosheet has a pair of end sidewalls that have a V-shaped undercut surface. A functional gate structure is located around the plurality of stacked and suspended semiconductor nanosheets, and a source/drain (S/D) semiconductor material structure is located on each side of the functional gate structure. In accordance with the present application, sidewall portions of each S/D semiconductor material structure are in direct contact with the V-shaped undercut surface of the end sidewalls of each of the semiconductor nanosheets.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Patent number: 10388576
    Abstract: A complementary metal-oxide-semiconductor field-effect transistor (CMOS) device includes a first source/drain (S/D) region and a second S/D region different from the first S/D region. A first epitaxy film formed of a first semiconductor material is on the first S/D region. A second epitaxy film formed of a second semiconductor material is on the second S/D region. The CMOS device further includes first and second S/D contact stacks. The first S/D contact stack includes a first contact trench liner having a first inner side wall extending from a first base portion to an upper surface of the first S/D contact stack. The second S/D contact stack includes a second contact trench liner having a second inner side wall extending from a second base portion to an upper surface of the second S/D contact stack. The first inner sidewall directly contacts the second inner sidewall.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: August 20, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
  • Patent number: 10373956
    Abstract: Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: August 6, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Rajesh N. Gupta, Farid Nemati, Scott T. Robins
  • Patent number: 10366942
    Abstract: A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding wires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: July 30, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Isao Ozawa
  • Patent number: 10347702
    Abstract: Provided are a flexible thin film transistor substrate and a flexible organic light emitting display device. The flexible thin film transistor substrate includes: a flexible substrate including at least one thin film transistor (TFT) area and having flexibility, an active layer disposed in the TFT area on the flexible substrate, a gate insulation layer disposed on the active layer, a gate electrode overlapping with the active layer on the gate insulation layer, an insulating interlayer disposed on the gate electrode, and a source electrode and a drain electrode disposed on the insulating interlayer and connected with the active layer, respectively. The gate insulation layer or the insulating interlayer includes at least one hole pattern configured to reduce bending stress.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: July 9, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Sangcheon Youn, NackBong Choi, YoonDong Cho
  • Patent number: 10340375
    Abstract: The present invention provides an epitaxial substrate for field effect transistor. In the epitaxial substrate for field effect transistor, a nitride-based Group III-V semiconductor epitaxial crystal containing Ga is interposed between the ground layer and the operating layer, and the nitride-based Group III-V semiconductor epitaxial crystal includes the following (i), (ii) and (iii). (i) a first buffer layer containing Ga or Al and containing a high resistivity crystal layer having added thereto compensation impurity element present in the same period as Ga in the periodic table and having small atomic number; (ii) a second buffer layer containing Ga or Al, laminated on the operating layer side of the first buffer layer; and (iii) a high purity epitaxial crystal layer containing acceptor impurities in a slight amount such that non-addition or depletion state can be maintained, provided between the high resistivity layer and the operating layer.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: July 2, 2019
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Masahiko Hata, Hiroyuki Sazawa, Naohiro Nishikawa
  • Patent number: 10319751
    Abstract: The present invention provides a display substrate and a manufacturing method thereof, and a flexible display device having the display substrate, which belong to the field of display technology, and can solve the problem of poor reliability of display substrates due to the damage to thin film transistors when the existing display substrates are bent. In the display substrate provided by the present invention, by introducing stress absorption units made of resin material into the display substrate, the stress generated by the display substrate being bent is released by the resin material, and thin film transistors on the display substrate are thus less likely to be damaged, so that the reliability of the whole display substrate is improved.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: June 11, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Hongfei Cheng, Yuxin Zhang
  • Patent number: 10312374
    Abstract: The present invention provides a circuit substrate exhibiting an excellent transmittance and being capable of suitably repair broken conductive lines; and a display device.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: June 4, 2019
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Ryohki Itoh
  • Patent number: 10312332
    Abstract: A semiconductor device is provided, which includes a substrate, a gate and a gate contact. The substrate has a well region, which has a source, a drain and a channel region extending between the source and the drain. The gate is on the well region and extends across the channel region. The gate contact is directly on the gate and vertically overlaps with the channel region. The gate contact has a strip shape of which a ratio of a length to a width is at least 2. The gate contact includes a gate conductive plug and a gate contact dielectric. The gate conductive plug directly contacts the gate. The gate contact dielectric surrounds side surfaces of the gate conductive plug and has a frame shape. A dielectric constant of the gate contact dielectric is substantially greater than 4.9.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: June 4, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 10312233
    Abstract: A semiconductor device includes a base region of second conductivity type formed on a drift layer of first conductivity type, a source region of first conductivity type located in the base region, a trench passing through the base region and the source region and dividing cell regions in plan view, a protective diffusion layer of second conductivity type disposed on a bottom of the trench, a gate electrode embedded in the trench with a gate insulating film therebetween, a source electrode electrically connected to the source region, and a protective contact region disposed at each of positions of three or more cell regions and connecting the protective diffusion layer and the source electrode to each other. The protective contact regions are disposed such that a triangle whose vertices are centers of three protective contact regions located closest to one another is an acute triangle.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: June 4, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Katsutoshi Sugawara, Yasuhiro Kagawa, Rina Tanaka, Yutaka Fukui
  • Patent number: 10290637
    Abstract: A conductive strap structure in lateral contact with a top semiconductor layer is formed on an inner electrode of a deep trench capacitor. A cavity overlying the conductive strap structure is filled a dielectric material to form a dielectric capacitor cap having a top surface that is coplanar with a topmost surface of an upper pad layer. A semiconductor mandrel in lateral contact with the dielectric capacitor cap is formed. The combination of the dielectric capacitor cap and the semiconductor mandrel is employed as a protruding structure around which a fin-defining spacer is formed. The semiconductor mandrel is removed, and the fin-defining spacer is employed as an etch mask in an etch process that etches a lower pad layer and the top semiconductor layer to form a semiconductor fin that laterally wraps around the conductive strap structure. An access finFET is formed employing two parallel portions of the semiconductor fin.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: May 14, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Felix Beaudoin, Stephen M. Lucarini, Xinhui Wang, Xinlin Wang
  • Patent number: 10290721
    Abstract: The invention provides a method of fabricating an electromechanical structure presenting a first substrate including a layer of monocrystalline material covered in a sacrificial layer that presents a free surface, the structure presenting a mechanical reinforcing pillar in the sacrificial layer, the method including etching a well region in the sacrificial layer to define a mechanical pillar; depositing a first functionalization layer of the first material to at least partially fill the well region and cover the free surface of the sacrificial layer around the well region; depositing a second material different from the first material for terminating the filling of the well region to thereby cover the first functionalization layer around the well region, planarizing the filler layer, the pillar being formed by the superposition of the first material and second material in the well region; and releasing the electromechanical structure by removing at least partially the sacrificial layer.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: May 14, 2019
    Assignee: Commissariat a L'Energie Atomique et aux Energies Alternatives
    Inventors: Vincent Larrey, Francois Perruchot, Bernard Diem, Laurent Clavelier, Philippe Robert
  • Patent number: 10283437
    Abstract: Methods, a computer readable medium, and an apparatus are provided. A method includes and the computer readable medium is configured for decomposing an overall pattern into a first mask pattern that includes a power rail base pattern and into a second mask pattern, and generating on the second mask pattern a power rail insert pattern that is at least partially aligned with the power rail base pattern of the first mask pattern. The apparatus is produced by photolithography using photolithographic masks generated by the method.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: May 7, 2019
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Richard T. Schultz, Omid Rowhani, Charles P. Tung
  • Patent number: 10283650
    Abstract: Certain aspects of the present disclosure generally relate to a semiconductor variable capacitor offering at least two types of capacitance tuning, as well as techniques for fabricating the same. For example, a CMOS-compatible silicon on insulator (SOI) process with a buried oxide (BOX) layer may provide a transcap with a front gate (above the BOX layer) and a back gate (beneath the BOX layer). The front gate may offer lower voltage, coarse capacitance tuning, whereas the back gate may offer higher voltage, fine capacitance tuning. By offering both types of capacitance tuning, such transcaps may provide greater capacitance resolution. Several variations of transcaps with front gate and back gate tuning are illustrated and described herein.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: May 7, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Bin Yang, Gengming Tao
  • Patent number: 10283374
    Abstract: Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: May 7, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michel J. Abou-Khalil, Robert J. Gauthier, Jr., Tom C. Lee, Junjun Li, Souvick Mitra, Christopher S. Putnam, Robert R. Robison
  • Patent number: 10273147
    Abstract: A MEMS and a method of manufacturing MEMS components are provided. The method includes providing a MEMS wafer stack including a top cap wafer, a MEMS wafer and optionally a bottom cap wafer. The MEMS wafer has MEMS structures patterned therein. The MEMS wafer and the cap wafers include insulated conducting channels forming insulated conducting pathways extending within the wafer stack. The wafer stack is bonded to an integrated circuit wafer having electrical contacts on its top side, such that the insulated conducting pathways extend from the integrated circuit wafer to the outer side of the top cap wafer. Electrical contacts on the outer side of the top cap wafer are formed and are electrically connected to the respective insulated conducting channels of the top cap wafer. The MEMS wafer stack and the integrated circuit wafer are then diced into components having respective sealed chambers and MEMS structures housed therein.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: April 30, 2019
    Assignee: Motion Engine Inc.
    Inventor: Robert Mark Boysel