Patents Examined by Meiya Li
  • Patent number: 11227848
    Abstract: A chip package array including a plurality of chip packages is provided. The chip packages are suitable for array arrangement to form the chip package array. Each of the chip packages includes a redistribution structure, a supporting structure, a chip, and an encapsulated material. The supporting structure is disposed on the redistribution structure and has an opening. The chip is disposed on the redistribution structure and located in the opening. The encapsulated material is located between the opening and the chip, wherein the encapsulated material is filled between the opening and the chip, and the chip and the supporting structure are respectively connected to the redistribution structure.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: January 18, 2022
    Assignee: VIA Alliance Semiconductor Co., Ltd.
    Inventors: Wen-Yuan Chang, Wei-Cheng Chen, Hsueh-Chung Shelton Lu
  • Patent number: 11227898
    Abstract: A display apparatus includes: a first substrate having a front surface and a rear surface; a first display layer disposed on the front surface of the first substrate, the first display layer configured to emit light in a front direction; a second display layer disposed on the rear surface of the first substrate, the second display layer configured to emit light in a rear direction; and a pressure sensor disposed on the rear surface of the first substrate, the pressure sensor configured to sense a pressure of a touch of a user.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: January 18, 2022
    Inventors: Seung Lyong Bok, Hee June Kwak, Mu Gyeom Kim, Min Soo Kim, Won Ki Hong
  • Patent number: 11227919
    Abstract: A field-effect-transistor includes forming a fin structure on a substrate, a gate structure formed across each fin structure and covering a portion of top and sidewall surfaces of the fin structure, a first doped layer, made of a first semiconductor material and doped with first doping ions, in each fin structure on one side of the corresponding gate structure, and a second doped layer, made of a second semiconductor material, doped with second doping ions, and having doping properties different from the first doped layer, in each fin structure on another side of the corresponding gate structure.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: January 18, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Xi Lin, Yi Hua Shen, Jian Pan
  • Patent number: 11222915
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a plurality of interconnect layers within a dielectric structure over an upper surface of a substrate. A passivation structure is formed over the dielectric structure. The passivation structure has sidewalls and a horizontally extending surface defining has a recess within an upper surface of the passivation structure. A bond pad is formed having a lower surface overlying the horizontally extending surface and one or more protrusions extending outward from the lower surface. The one or more protrusions extend through one or more openings within the horizontally extending surface to contact a first one of the plurality of interconnect layers. An upper passivation layer is deposited on sidewalls and an upper surface of the bond pad and on sidewalls and the upper surface of the passivation structure.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: January 11, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Chun Hsu, Ching-Chun Wang, Dun-Nian Yaung, Jeng-Shyan Lin, Shyh-Fann Ting
  • Patent number: 11222866
    Abstract: A package structure includes: 1) a circuit substrate; 2) a first semiconductor device disposed on the circuit substrate; 3) a first insulation layer covering a sidewall of the first semiconductor device; 4) a second insulation layer covering the first insulation layer; and 5) a third insulation layer disposed on the circuit substrate and in contact with the second insulation layer.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: January 11, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chi-Chih Shen, Jen-Chuan Chen, Tommy Pan
  • Patent number: 11222900
    Abstract: According to one embodiment, a semiconductor memory device includes: a first interconnect layer including a first electrode that extends in a first direction and a second electrode that extends in a second direction and is in contact with one end of the first electrode; a second interconnect layer including a third electrode that is provided adjacently to the first electrode and a fourth electrode that is in contact with one end of the third electrode; a first semiconductor layer provided between the first electrode and the third electrode; a first charge storage layer provided between the first semiconductor layer and the first electrode; a second charge storage layer provided between the first semiconductor layer and the third electrode; and a first bit line provided above the first semiconductor layer and extending in the first direction.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: January 11, 2022
    Assignee: Toshiba Memory Corporation
    Inventors: Yoshiro Shimojo, Tomoya Sanuki
  • Patent number: 11217650
    Abstract: A display unit includes a substrate, a first electrode, a second electrode, an organic layer, and an auxiliary electrically-conductive layer. The substrate includes a pixel region including a plurality of pixels and a peripheral region outside the pixel region. The first electrode is provided for each of the plurality of pixels in the pixel region on the substrate. The second electrode is opposed to the first electrode, and is provided common for the plurality of pixels. The organic layer is provided between the second electrode and the first electrode, and includes a light-emitting layer. The auxiliary electrically-conductive layer includes an organic electrically-conductive material, and the auxiliary electrically-conductive layer is disposed in the pixel region on the substrate and is electrically coupled to the second electrode.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: January 4, 2022
    Assignee: JOLED INC.
    Inventors: Yasuhiro Terai, Yasuharu Shinokawa, Jiro Yamada, Atsuhito Murai, Masahiko Kondo, Noriteru Maeda
  • Patent number: 11201242
    Abstract: A semiconductor structure is provided that includes non-metal semiconductor alloy containing contact structures for field effect transistors (FETs), particularly p-type FETs. Notably, each non-metal semiconductor alloy containing contact structure includes a highly doped epitaxial semiconductor material directly contacting a topmost surface of a source/drain region of the FET, a titanium liner located on the highly doped epitaxial semiconductor material, a diffusion barrier liner located on the titanium liner, and a contact metal portion located on the diffusion barrier liner.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: December 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Keith E. Fogel, Nicole S. Munro, Alexander Reznicek
  • Patent number: 11189766
    Abstract: Solid-state lighting devices including light-emitting diodes (LEDs) and LED packages are disclosed. LED packages are provided with improved thermal and/or electrical coupling between LED chips and submounts or lead frames. Various configurations of submounts with via arrangements are disclosed to provide improved coupling between LED chips and submounts. LED chip contacts are disclosed with one or more openings that are registered with vias to provide more uniform mounting. Multiple LED chips may be arranged around a thermally conductive element on a submount, and a via in the submount may be registered with the thermally conductive element. Subassemblies are provided between LED chips and lead frames to improve electrical and thermal coupling. Underfill materials may be arranged between LED chips and lead frames to provide improved mechanical support.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: November 30, 2021
    Assignee: CreeLED, Inc.
    Inventors: Arthur F. Pun, Colin Blakely, Kyle Damborsky, Jae-Hyung Jeremiah Park
  • Patent number: 11189642
    Abstract: To provide a highly reliable semiconductor device including an oxide semiconductor. Further to provide a highly reliable light-emitting device including an oxide semiconductor. A second electrode sealed together with a semiconductor element including an oxide semiconductor hardly becomes inactive. A hydrogen ion and/or a hydrogen molecule produced by reaction of the active second electrode with moisture remaining in the semiconductor device and/or moisture entering from the outside of the device increase the carrier concentration in the oxide semiconductor, which causes a reduction in the reliability of the semiconductor device. An adsorption layer of a hydrogen ion and/or a hydrogen molecule may be provided on the other surface side of the second electrode having one surface in contact with the organic layer. Further, an opening which a hydrogen ion and/or a hydrogen molecule passes through may be provided for the second electrode.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: November 30, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kaoru Hatano
  • Patent number: 11189753
    Abstract: A solid state light sheet and method of fabricating the sheet are disclosed. In one embodiment, bare LED chips have top and bottom electrodes, where the bottom electrode is a large reflective electrode. The bottom electrodes of an array of LEDs (e.g., 500 LEDs) are bonded to an array of electrodes formed on a flexible bottom substrate. Conductive traces are formed on the bottom substrate connected to the electrodes. A transparent top substrate is then formed over the bottom substrate. Various ways to connect the LEDs in series are described along with many embodiments. In one method, the top substrate contains a conductor pattern that connects to LED electrodes and conductors on the bottom substrate.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: November 30, 2021
    Assignee: Quarkstar LLC
    Inventors: Louis Lerman, Allan Brent York, Michael David Henry, Robert V. Steele, Brian D. Ogonowsky
  • Patent number: 11183496
    Abstract: Semiconductor devices are provided. The semiconductor device includes an active fin which extends along a first direction and has a protruding shape, a gate structure which is disposed on the active fin to extend along a second direction intersecting the first direction, and a spacer which is disposed on at least one side of the gate structure, wherein the gate structure includes a first area and a second area which is adjacent to the first area in the second direction, wherein a first width of the first area in the first direction is different from a second width of the second area in the first direction, and the spacer extends continuously along both the first area and the second area.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: November 23, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ju-Youn Kim, Hyun-Jo Kim, Hwa-Sung Rhee
  • Patent number: 11164966
    Abstract: Disclosed herein are single electron transistor (SET) devices, and related methods and devices. In some embodiments, a SET device may include: first and second source/drain (S/D) electrodes; a plurality of islands, disposed between the first and second S/D electrodes; and dielectric material disposed between adjacent ones of the islands, between the first S/D electrode and an adjacent one of the islands, and between the second S/D electrode and an adjacent one of the islands.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: November 2, 2021
    Assignee: Intel Corporation
    Inventors: Hubert C. George, James S. Clarke
  • Patent number: 11164883
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack. Each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. The electrically conductive layers include aluminum and silicon and provide low resistance electrically conductive paths as word lines of the three-dimensional memory device. The aluminum-based electrically conductive layers can provide low resistivity, low mechanical stress, and thermal stability for use as high performance word lines.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: November 2, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Peter Rabkin, Masaaki Higashitani, Jayavel Pachamuthu
  • Patent number: 11164890
    Abstract: A semiconductor structure includes layer stack structures laterally extending along a first horizontal direction and spaced apart from each other along a second horizontal direction by line trenches. Each of the layer stack structures includes at least one instance of a unit layer sequence that includes, from bottom to top or top to bottom, a doped semiconductor source strip, a channel-level insulating strip, and a doped semiconductor drain strip. Line trench fill structures are located within a respective one of the line trenches. Each of the line trench fill structures includes a laterally-alternating sequence of memory pillar structures and dielectric pillar structures. Each of the memory pillar structures includes a gate electrode, at least one pair of ferroelectric dielectric layers, and at least one pair of vertical semiconductor channels located at each level of the channel-level insulating strips.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: November 2, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yanli Zhang, Johann Alsmeier, Fei Zhou
  • Patent number: 11158533
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a first trench, and a second trench. The substrate has a first region and a second region. The first trench is formed in the substrate within the first region. The first trench is surrounded by a first protrusion structure having a top portion and sidewalls. The second trench is formed in the substrate within the second region. The second trench is surrounded by a second protrusion structure having a top portion and sidewalls. The second trench is deeper than the first trench. The connection portion between the top portion and the sidewalls of the second protrusion structure has a greater radius of curvature than the connection portion between the top portion and the sidewalls of the first protrusion structure.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: October 26, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Ching-Yi Hsu, Pi-Kuang Chuang, Po-Sheng Hu
  • Patent number: 11158626
    Abstract: A semiconductor integrated circuit device may include a pad, a first voltage protection unit and a second voltage protection unit. The first voltage protection unit may be connected with the pad. The first voltage protection unit may be configured to maintain a turn-off state when a test voltage having a negative level may be applied from the pad. The second voltage protection unit may be connected between the first voltage protection unit and a ground terminal. The second voltage protection unit may be turned-on when an electrostatic voltage having a positive level may be applied from the pad. The second voltage protection unit may include a plurality of gate positive p-channel metal oxide semiconductor (GPPMOS) transistors serially connected with each other.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: October 26, 2021
    Assignee: SK hynix Inc.
    Inventors: Chang Hwi Lee, Hee Jeong Son, Ki Ryong Jung, Seung Yeop Lee
  • Patent number: 11158563
    Abstract: A power semiconductor module including a cooling apparatus and a power semiconductor device mounted on the cooling apparatus, wherein the cooling apparatus includes: a ceiling plate that; a case; and a cooling fin, a ceiling plate and the case respectively include fastening portions that are used to fasten the ceiling plate and the case to an external apparatus, while the ceiling plate and the outer edge portion are arranged in an overlapping manner, the power semiconductor device includes a circuit substrate and a terminal case, the fastening portions protrude farther outward than a periphery of the ceiling plate, and the terminal case includes a case body arranged along a perimeter of the circuit substrate and reinforcing portions that extend to top surface sides of the fastening portions.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: October 26, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hiromichi Gohara, Takafumi Yamada, Yuta Tamai
  • Patent number: 11145617
    Abstract: A semiconductor structure includes a substrate, a chip, a plurality of conductive bumps, a flexible printed circuit (FPC) board and a plurality of circuit patterns. The chip is disposed on the substrate and includes a plurality of pads. The conductive bumps are disposed on the pads respectively. The FPC board is connected between the substrate and the chip, and the conductive bumps penetrate through an end of the FPC board. The circuit patterns are disposed on the FPC board and electrically connected to the conductive bumps and the substrate.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: October 12, 2021
    Assignee: Winbond Electronics Corp.
    Inventor: Yu-Ming Chen
  • Patent number: 11145812
    Abstract: A resistive random access memory device includes a first electrode; a solid electrolyte made of metal oxide extending onto the first electrode; a second electrode able to supply mobile ions circulating in the solid electrolyte made of metal oxide to the first electrode to form a conductive filament between the first and second electrodes when a voltage is applied between the first and second electrodes; an interface layer including a transition metal from groups 3, 4, 5 or 6 of the periodic table and a chalcogen element; the interface layer extending onto the solid electrolyte made of metal oxide, the second electrode extending onto the interface layer.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: October 12, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Gabriel Molas, Philippe Blaise, Faiz Dahmani, Elisa Vianello