Patents Examined by Meiya Li
  • Patent number: 10818584
    Abstract: A package substrate including a redistribution structure and a core is provided. The redistribution structure has a first redistribution surface and a bonding pad disposed on the first redistribution surface. The core is disposed on the redistribution structure and has a first core surface facing towards the first redistribution surface of the redistribution structure. The core has a first core pad disposed on the first core surface and directly bonded to the bonding pad, and the first core pad is offset from the bonding pad. A package structure is also provided.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: October 27, 2020
    Inventor: Dyi-Chung Hu
  • Patent number: 10811495
    Abstract: Fabrication of a semiconductor structure includes forming a set of two or more fins on a source/drain region formed on a substrate. A first mask layer and a second mask layer are formed on each fin. A spacer layer is formed on the source/drain region and between each fin, and a dielectric layer is formed on the spacer layer and along an exterior of each fin. A plurality of gate metal portions is created each having a thickness about equal to a target thickness. The first mask layer and an exposed portion of the dielectric layer are removed from each fin. An interlayer dielectric is deposited on the semiconductor structure. Portions of the interlayer dielectric and the gate metal are removed to a top of the second mask layer. The gate metal portions are each recessed to substantially the same depth.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: October 20, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10804375
    Abstract: A method for manufacturing a semiconductor device is provided by follows. A fin is formed over a substrate. A spacer is formed on a sidewall of a first portion of the fin. An epitaxy feature is grown from a second portion of the fin that is in a position lower than the first portion of the fin, in which the forming the epitaxy feature is performed after the forming the spacer. The spacer is removed to expose the first portion of the fin. A gate stack is formed around the exposed first portion of the fin.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: October 13, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Sheng Yun, Shao-Ming Yu, Tung-Ying Lee, Chih-Chieh Yeh
  • Patent number: 10797065
    Abstract: A nonvolatile semiconductor storage device including a number of memory cells formed on a semiconductor substrate, each of the memory cells has a tunnel insulating film, a charge storage layer, a block insulating film, and a gate electrode which are formed in sequence on the substrate. The gate electrode is structured such that at least first and second gate electrode layers are stacked. The dimension in the direction of gate length of the second gate electrode layer, which is formed on the first gate electrode layer, is smaller than the dimension in the direction of gate length of the first gate electrode layer.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: October 6, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Toshitake Yaegashi
  • Patent number: 10797054
    Abstract: It is an object to provide a memory device whose power consumption can be suppressed and a semiconductor device including the memory device. As a switching element for holding electric charge accumulated in a transistor which functions as a memory element, a transistor including an oxide semiconductor film as an active layer is provided for each memory cell in the memory device. The transistor which is used as a memory element has a first gate electrode, a second gate electrode, a semiconductor film located between the first gate electrode and the second gate electrode, a first insulating film located between the first gate electrode and the semiconductor film, a second insulating film located between the second gate electrode and the semiconductor film, and a source electrode and a drain electrode in contact with the semiconductor film.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: October 6, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yutaka Shionoiri, Hiroyuki Miyake, Kiyoshi Kato
  • Patent number: 10790240
    Abstract: A hybrid-bonding structure and a method for forming a hybrid-bonding structure are provided. The hybrid-bonding structure includes a first semiconductor substrate, a first conductive line and a first dielectric dummy pattern. The first conductive line is formed over the first semiconductor substrate. A surface of the first conductive line is configured to hybrid-bond with a second conductive line over a second semiconductor substrate. The first dielectric dummy pattern is formed over the first semiconductor substrate and embedded in the first conductive line.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Ming Wu, Kuan-Liang Liu, Pao-Tung Chen
  • Patent number: 10784251
    Abstract: An integrated circuit includes a plurality of first n-type regions and a plurality of second n-type regions that each intersect a surface of a substrate. The first n-type regions are arranged in a first linear array within a first n-well and a second linear array within a second n-well. The first and second n-wells are each located within and separated by a first p-type region. The second n-type regions are located within and separated by a second p-type region. An n-type trench region is located between the first and second p-type regions. The n-type trench region extends into the substrate toward an n-type buried layer that extends under the first p-type region and the second p-type region.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: September 22, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Henry Litzmann Edwards, Akram Ali Salman
  • Patent number: 10777643
    Abstract: A semiconductor device includes: a semiconductor substrate; a buffer layer provided on the semiconductor substrate; a GaN channel layer provided on the buffer layer; an AlGaN electron travel layer provided on the GaN channel layer; a GaN cap layer provided on the AlGaN electron travel layer, having a nitrogen polarity, and on which a plurality of recesses are formed; and a gate electrode, a source electrode and a drain electrode provided in each of the plurality of recesses.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: September 15, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventor: Kohei Miki
  • Patent number: 10777623
    Abstract: Disclosed is an electronic device including a housing, a display panel, and an image sensor. The display panel includes a first polarization layer that causes light input from outside the electronic device to oscillate in a first direction as a first linearly-polarized light, a first retardation layer disposed below the first polarization layer and causing at least a portion of the first linearly-polarized light to oscillate as a circularly-polarized light, a substrate layer disposed below the first retardation layer and passing at least a portion of the circularly-polarized light, and a protection layer disposed below the substrate layer and protecting at least a portion of the substrate layer by covering the portion of the substrate layer.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: September 15, 2020
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Bong Jae Rhee, Song Hee Jung, Hyun Chang Shin, Hyun Woo Kim, Ji Hoon Park, Ji Hun Heo
  • Patent number: 10755949
    Abstract: Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an cathode on a substrate and a anode on the substrate. The anode is in electrical contact with the cathode. The method further includes forming a device between the cathode and the anode. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: August 25, 2020
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Michel J. Abou-Khalil, Robert J. Gauthier, Jr., Tom C. Lee, Junjun Li, Souvick Mitra, Christopher S. Putnam, Robert R. Robison
  • Patent number: 10756206
    Abstract: A compound semiconductor field effect transistor may include a channel layer. The compound semiconductor transistor may also include a multi-layer epitaxial barrier layer on the channel layer. The channel layer may be on a doped buffer layer or on a first un-doped buffer layer. The compound semiconductor field effect transistor may further include a gate. The gate may be on a first tier of the multi-layer epitaxial barrier layer, and through a space between portions of a second tier of the multi-layer epitaxial barrier layer.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: August 25, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Bin Yang, Xia Li, Gengming Tao, Periannan Chidambaram
  • Patent number: 10707188
    Abstract: There is presented a light emitting device, having plural light emitting elements disposed on a substrate, in which a protection element, such as a zener diode, can be disposed at an appropriate position. The light emitting device includes: a substrate; a light emitting section having plural light emitting elements disposed in a mounting area on the substrate; a positive electrode and negative electrode each having a pad section and wiring section to apply voltage to the light emitting section through the wiring sections; a protection element disposed at one of the positive electrode and negative electrode and electrically connected with the other one electrode; and a light reflecting resin formed on the substrate such as to cover at least the wiring sections and the protection element, wherein the wiring sections are formed along the periphery of the mounting area such that one end portions thereof are adjacent to each other.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: July 7, 2020
    Assignee: NICHIA CORPORATION
    Inventor: Haruaki Sasano
  • Patent number: 10707438
    Abstract: A light emitting display device includes a substrate including a plurality of sub pixel areas having an emission area and an anode contact area, a driving thin film transistor disposed in each of the plurality of sub pixel areas, a planarization layer disposed on the substrate, a cathode electrode disposed on the planarization layer overlapped with the emission area, a plurality of connection electrode patterns disposed on the planarization layer overlapped with the anode contact area, and connected with respective source electrodes of the driving thin film transistors disposed in the plurality of sub pixel areas by one-to-one correspondence, an emission layer disposed on the cathode electrode, and a plurality of anode electrodes disposed on the emission layer, and connected with the plurality of connection electrode patterns through the anode contact area by one-to-one correspondence.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: July 7, 2020
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Hoiyong Kwon, SeYeoul Kwon
  • Patent number: 10707327
    Abstract: A semiconductor device includes a semiconductor substrate including a doped region. A metal layer is formed on the doped region. An insulating layer covers the metal layer. The metal layer can serve as a buried metal layer which reduces electrical resistance between electrical charge in the doped region and adjacent contacts. The contacts can extend through the insulating layer between the buried metal layer and overlying metal stripes.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: July 7, 2020
    Assignee: Great Wall Semiconductor Corporation
    Inventors: Patrick M. Shea, David N. Okada, Samuel J. Anderson
  • Patent number: 10699901
    Abstract: A method of scaling a nonvolatile trapped-charge memory device and the device made thereby is provided. In an embodiment, the method includes forming a channel region including polysilicon electrically connecting a source region and a drain region in a substrate. A tunneling layer is formed on the substrate over the channel region by oxidizing the substrate to form an oxide film and nitridizing the oxide film. A multi-layer charge trapping layer including an oxygen-rich first layer and an oxygen-lean second layer is formed on the tunneling layer, and a blocking layer deposited on the multi-layer charge trapping layer. In one embodiment, the method further includes a dilute wet oxidation to densify a deposited blocking oxide and to oxidize a portion of the oxygen-lean second layer.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: June 30, 2020
    Assignee: LONGITUDE FLASH MEMORY SOLUTIONS LTD.
    Inventors: Frederick B. Jenne, Sagy Charel Levy, Krishnaswamy Ramkumar
  • Patent number: 10692785
    Abstract: A semiconductor pattern for monitoring overlay and critical dimension at post-etching stage is provided in the present invention, which include a first inverted-T shaped pattern with a base portion and a middle portion extending from the base portion and a second pattern adjacent and spaced apart from the base portion of the first inverted-T shaped pattern, wherein the first inverted-T shaped pattern and the second pattern are composed of a plurality of spacer patterns spaced apart from each other.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: June 23, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chien-Hao Chen, Chien-Wei Huang, Chia-Hung Wang, Sho-Shen Lee
  • Patent number: 10692841
    Abstract: Semiconductor devices having through-stack interconnects for facilitating connectivity testing, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a stack of semiconductor dies and a plurality of through-stack interconnects extending through the stack to electrically couple the semiconductor dies. The interconnects include functional interconnects and at least one test interconnect. The test interconnect is positioned in a portion of the stack more prone to connectivity defects than the functional interconnects. Accordingly, testing the connectivity of the test interconnect can provide an indication of the connectivity of the functional interconnects.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: June 23, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Christian N. Mohr, Scott E. Smith
  • Patent number: 10686125
    Abstract: The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes a dielectric protection layer disposed over a dielectric structure that laterally surrounds one or more conductive interconnect layers. The dielectric protection layer has a protrusion extending outward from an upper surface of the dielectric protection layer. A bottom electrode is disposed over the dielectric protection layer and has sidewalls extending outward from a lower surface of the bottom electrode through the dielectric protection layer. The bottom electrode has a substantially planar upper surface over the protrusion. A data storage element is over the substantially planar upper surface of the bottom electrode, and a top electrode is over the data storage element.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Harry-Hak-Lay Chuang, Hung Cho Wang, Tong-Chern Ong, Wen-Ting Chu, Yu-Wen Liao, Kuei-Hung Shen, Kuo-Yuan Tu, Sheng-Huang Huang
  • Patent number: 10629690
    Abstract: A semiconductor device includes a transistor in a semiconductor substrate. The transistor includes a drift zone of a first conductivity type adjacent to a drain region, and a first field plate and a second field plate adjacent to the drift zone. The second field plate is arranged between the first field plate and the drain region. The second field plate is electrically connected to a contact portion arranged in the drift zone. The transistor further includes an intermediate portion of the first conductivity type at a lower doping concentration than the drift zone. A distance between the intermediate portion and the drain region is smaller than the distance between the contact portion and the drain region.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: April 21, 2020
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Franz Hirler, Till Schloesser
  • Patent number: 10615159
    Abstract: Embodiments are directed to devices and methods for integrating laterally diffused metal oxide semiconductor (LDMOS) technology on vertical field effect transistor (VFET) technology, which enables VFET applications to be broadened to include power amplifiers. By providing a combined asymmetric underlapped drain, high current, low subthreshold slope and LDMOS lightly doped drain, high drain resistance and high drain voltage are enabled.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: April 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang