Patents Examined by Meiya Li
  • Patent number: 11545443
    Abstract: A method for forming a hybrid-bonding structure is provided. The method includes forming a first dielectric layer over a first semiconductor substrate. The first semiconductor substrate includes a conductive structure. The method also includes partially removing the first dielectric layer to form a first dielectric dummy pattern, a second dielectric dummy pattern and a third dielectric dummy pattern and an opening through the first dielectric layer. The first dielectric dummy pattern, the second dielectric dummy pattern and the third dielectric dummy pattern are surrounded by the opening. In addition, the method includes forming a first conductive line in the opening. The first conductive line is in contact with the conductive structure.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: January 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Ming Wu, Kuan-Liang Liu, Pao-Tung Chen
  • Patent number: 11545412
    Abstract: A package structure including a circuit board and a heat generating element is provided. The circuit board includes a plurality of circuit layers and a composite material layer. A thermal conductivity of the composite material layer is between 450 W/mK and 700 W/mK. The heat generating element is disposed on the circuit board and electrically connected to the circuit layers. Heat generated by the heat generating element is transmitted to an external environment through the composite material layer.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: January 3, 2023
    Assignee: Unimicron Technology Corp.
    Inventors: Pei-Wei Wang, Ching Sheng Chen, Ra-Min Tain, Ming-Hao Wu, Hsuan-Wei Chen
  • Patent number: 11508754
    Abstract: A semiconductor memory structure includes a substrate, two doped regions in the substrate, a plurality of gate layers, a plurality of insulating layers, a column over the substrate, a charge-trapping layer, and a channel layer. The substrate includes dopants of a first conductivity type, and the two doped regions include dopants of a second conductivity type complementary to the first conductivity type. The gate layers and the insulating layers are alternately stacked over the substrate. The column penetrates the gate layers and the insulating layers, and includes an isolation structure, a source structure and a drain structure. at two sides of the isolation structure. The charge-trapping layer is at two sides of the column, and the channel layer is between the charge-trapping layer and the column. A bottom surface of the charge-trapping layer is in contact with the substrate and separated from the two doped regions.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Nuo Xu, Sai-Hooi Yeong, Yu-Ming Lin, Zhiqiang Wu
  • Patent number: 11495735
    Abstract: A spin-current magnetization rotational element includes: a ferromagnetic metal layer; and a spin-orbit torque wiring that extends in a first direction intersecting a stacking direction of the ferromagnetic metal layer and is bonded to the ferromagnetic metal layer. A direction of a spin injected into the ferromagnetic metal layer from the spin-orbit torque wiring intersects a magnetization direction of the ferromagnetic metal layer. The ferromagnetic metal layer has shape anisotropy and has a demagnetizing field distribution caused by the shape anisotropy. The demagnetizing field distribution generates an easy magnetization rotational direction in which the magnetization of the ferromagnetic metal layer is most easily reversed. The easy magnetization rotational direction intersects the first direction in a plan view seen from the stacking direction.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: November 8, 2022
    Assignee: TDK CORPORATION
    Inventors: Tatsuo Shibata, Tomoyuki Sasaki, Tohru Oikawa
  • Patent number: 11495577
    Abstract: Semiconductor devices having through-stack interconnects for facilitating connectivity testing, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a stack of semiconductor dies and a plurality of through-stack interconnects extending through the stack to electrically couple the semiconductor dies. The interconnects include functional interconnects and at least one test interconnect. The test interconnect is positioned in a portion of the stack more prone to connectivity defects than the functional interconnects. Accordingly, testing the connectivity of the test interconnect can provide an indication of the connectivity of the functional interconnects.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: November 8, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Christian N. Mohr, Scott E. Smith
  • Patent number: 11489118
    Abstract: A resistive random access memory (RRAM) device and a method for constructing the device is described. A capping layer structure is provided over a bottom contact where the capping layer includes a recess situated over the bottom contact. A first portion of the recess is filled with a lower electrode such that the width of the recess defines the width of the lower electrode. A second portion of the recess is filled with a high-K layer so that a bottom surface of the high-K layer has a stepped profile. A top electrode is formed on the high-K layer and a top contact is formed on the top electrode. The width of the high-K layer is greater than the width of the lower electrode to prevent shorting between the top contact and the lower electrode of the RRAM device.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: November 1, 2022
    Assignee: International Business Machines Corporation
    Inventors: Baozhen Li, Chih-Chao Yang, Ernest Y Wu, Andrew Tae Kim
  • Patent number: 11476121
    Abstract: A method provides a gate structure for a plurality of components of a semiconductor device. A silicate layer is provided. In one aspect, the silicate layer is provided on a channel of a CMOS device. A high dielectric constant layer is provided on the silicate layer. The method also includes providing a work function metal layer on the high dielectric constant layer. A low temperature anneal is performed after the high dielectric constant layer is provided. A contact metal layer is provided on the work function metal layer.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: October 18, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wei-E Wang, Mark S. Rodder, Borna J. Obradovic
  • Patent number: 11469212
    Abstract: A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias in a layer of a first semiconductor chip. The first plurality of conductive vias includes first ends and second ends. A first conductor pad is formed in ohmic contact with the first ends of the first plurality of conductive vias.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: October 11, 2022
    Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULC
    Inventors: Bryan Black, Michael Z. Su, Gamal Refai-Ahmed, Joe Siegel, Seth Prejean
  • Patent number: 11469385
    Abstract: A flexible display and a method of manufacturing the same are disclosed. In one aspect, the method includes forming a sacrificial metal layer over a support substrate, the sacrificial metal layer formed of a metal material, and forming a barrier layer over the sacrificial metal layer, the barrier layer formed of an organic material. The method also includes exposing the sacrificial metal layer to oxygen so as to form a sacrificial metal oxide layer, forming a display unit over the barrier layer, and separating the barrier layer from the support substrate.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: October 11, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jinhwan Choi, Kihyun Kim, Taean Seo
  • Patent number: 11469325
    Abstract: Provided in a semiconductor device including a substrate, an active region upwardly protruding from the substrate, a plurality of active fins upwardly protruding from the active region and extending in a first direction parallel to an upper surface of the substrate, the plurality of active fins being provided in a second direction that is parallel to the upper surface of the substrate and intersects with the first direction, and an isolation structure provided on the substrate, the isolation structure covering a sidewall of the active region and a lower portion of a sidewall of each of the plurality of active fins, wherein a first sidewall of the active region adjacent to a first active fin among the plurality of active fins has a staircase shape, the first active fin being provided on a first edge of the active region in the second direction.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: October 11, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Doo Jeon, Han-Wool Park, Se-Jin Park, No-Young Chung
  • Patent number: 11456176
    Abstract: A device includes a semiconductor substrate, a gate dielectric over the semiconductor substrate, and a gate electrode over the gate dielectric. The gate electrode has a first portion having a first thickness, and a second portion having a second thickness smaller than the first thickness. The device further includes a source/drain region on a side of the gate electrode with the source/drain region extending into the semiconductor substrate, and a device isolation region. The device isolation region has a part having a sidewall contacting a second sidewall of the source/drain region to form an interface. The interface is overlapped by a joining line of the first portion and the second portion of the gate electrode.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: September 27, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Min-Feng Kao, Szu-Ying Chen, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Feng-Chi Hung
  • Patent number: 11437397
    Abstract: A three-dimensional (3D) semiconductor memory device includes a source conductive pattern on a substrate and extending in parallel to a top surface of the substrate, and an electrode structure including an erase control gate electrode, a ground selection gate electrode, cell gate electrodes, and a string selection gate electrode, which are sequentially stacked on the source conductive pattern in a first direction perpendicular to the top surface of the substrate.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: September 6, 2022
    Inventors: Euntaek Jung, JoongShik Shin, SangJun Hong
  • Patent number: 11424176
    Abstract: A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding wires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: August 23, 2022
    Assignee: Kioxia Corporation
    Inventor: Isao Ozawa
  • Patent number: 11424246
    Abstract: It is an object to provide a memory device whose power consumption can be suppressed and a semiconductor device including the memory device. As a switching element for holding electric charge accumulated in a transistor which functions as a memory element, a transistor including an oxide semiconductor film as an active layer is provided for each memory cell in the memory device. The transistor which is used as a memory element has a first gate electrode, a second gate electrode, a semiconductor film located between the first gate electrode and the second gate electrode, a first insulating film located between the first gate electrode and the semiconductor film, a second insulating film located between the second gate electrode and the semiconductor film, and a source electrode and a drain electrode in contact with the semiconductor film.
    Type: Grant
    Filed: October 2, 2020
    Date of Patent: August 23, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yutaka Shionoiri, Hiroyuki Miyake, Kiyoshi Kato
  • Patent number: 11417793
    Abstract: Provided is a method of manufacturing a semiconductor optical device, which makes it possible to reduce the thickness of a semiconductor optical device including InGaAsP-based III-V compound semiconductor layers containing at least In and P to a thickness smaller than that of conventional devices, and provide a semiconductor optical device. The method of manufacturing a semiconductor optical device includes a step of forming a semiconductor laminate on the InP growth substrate; a step of bonding the semiconductor laminate to the support substrate formed from a Si substrate, with at least the metal bonding layer therebetween; and a step of removing the InP growth substrate.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: August 16, 2022
    Assignee: DOWA Electronics Materials Co., Ltd.
    Inventors: Jumpei Yamamoto, Tetsuya Ikuta
  • Patent number: 11410925
    Abstract: Various fuse structures are disclosed herein that exhibit improved performance, such as reduced electro-migration. An exemplary fuse structure includes an anode, a cathode, and a fuse link extending between the anode and the cathode. A plurality of anode contacts are coupled to the anode, and a plurality of cathode contacts are coupled to the cathode. The plurality of cathode contacts are arranged symmetrically with respect to a centerline of the fuse link.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shien-Yang Wu, Wei-Chang Kung
  • Patent number: 11387171
    Abstract: A method of packaging a semiconductor die includes connecting an interposer frame directly to a substrate, wherein the interposer frame has a plurality of conductive columns. The method further includes attaching the semiconductor die to the substrate in an opening of the interposer frame, wherein the semiconductor die directly contacts the substrate. The method further includes forming a molding compound to fill space between the semiconductor die and the interposer frame. The method further includes removing a portion of the molding compound to expose the plurality of conductive columns. The method further includes forming a redistribution layer directly contacting a top surface of the semiconductor die and a top surface of the interposer frame.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: July 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hui-Min Huang, Shou-Cheng Hu, Chih-Wei Lin, Ming-Da Cheng, Chung-Shi Liu, Chen-Shien Chen
  • Patent number: 11373990
    Abstract: A semiconductor device has a first semiconductor die including a first protection circuit. A second semiconductor die including a second protection circuit is disposed over the first semiconductor die. A portion of the first semiconductor die and second semiconductor die is removed to reduce die thickness. An interconnect structure is formed to commonly connect the first protection circuit and second protection circuit. A transient condition incident to the interconnect structure is collectively discharged through the first protection circuit and second protection circuit. Any number of semiconductor die with protection circuits can be stacked and interconnected via the interconnect structure to increase the ESD current discharge capability. The die stacking can be achieved by disposing a first semiconductor wafer over a second semiconductor wafer and then singulating the wafers. Alternatively, die-to-wafer or die-to-die assembly is used.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: June 28, 2022
    Assignee: Semtech Corporation
    Inventors: Changjun Huang, Jonathan Clark
  • Patent number: 11355642
    Abstract: Methods for manufacturing semiconductor structures are provided. The method includes forming a first masking layer over a substrate and forming a second masking layer over the first masking layer. The method includes forming a photoresist pattern over the second masking layer and patterning the second masking layer through the photoresist pattern. The method further includes diminishing the photoresist pattern and patterning the second masking layer and the first masking layer through the diminished photoresist pattern. The method further includes removing the diminished photoresist pattern and patterning the semiconductor substrate through the second masking layer and the first masking layer to form a fin structure. The method further includes forming a gate structure over the fin structure.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: June 7, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Ju-Wang Hsu, Chih-Yuan Ting, Tang-Xuan Zhong, Yi-Nien Su, Jang-Shiang Tsai
  • Patent number: 11355678
    Abstract: A light-emitting device includes: at least one light-emitting element; a first light-transmissive member covering the light-emitting element; a second light-transmissive member covering the first light-transmissive member; and a light-diffusing member in the second light-transmissive member. The light-diffusing member includes hollow particles. The second light-transmissive member has a bottom surface having irregularities due to presence of the light-diffusing member.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: June 7, 2022
    Assignee: Nichia Corporation
    Inventors: Shoichi Kashihara, Masanobu Sato, Tomohisa Kishimoto