Abstract: A method and device for synchronization of messages, wherein the phase of a reception clock signal is controlled in dependence on the phase of the messages received by causing the absolute value of the phase of the reception clock signal to vary by the quantity A.sub.i (2.pi./N) at the "i.sup.th " transition of the received message, the sequence .vertline.A.sub.i .vertline. being a sequence of decreasing whole numbers where i varies from 1 to p and 2.pi./N designates the elementary step of variation of phase of the reception clock signal. The device includes a read-only memory for storing the values A.sub.i.

Abstract: A microcode control mechanism is provided for producing the sequences of microwords used to control the execution of processor instructions in a microprogrammed data processor. This microcode control mechanism includes sequence counter circuitry for supplying a sequence of numbers and a programmable logic array mechanism responsive to the processor instruction and to the sequence of numbers for producing a sequence of microwords needed to execute the instruction. The microcode control mechanism also includes repeat circuitry responsive to a predetermined microword produced by the programmable logic array mechanism for setting the sequence counter circuitry back to a count which is less than the current count for causing a selected portion of the microword sequence to be repeated. The microcode control mechanism further includes a programmable repeat counter for counting the number of times the selected portion is repeated and for disabling the repeating action after a selected number of repeats.

Abstract: A magnetic tape drive capable of simulating the performance of a fast acceleration start/stop tape drive without a capstan drive or vacuum columns. A streaming type tape drive is provided with a semiconductor cache memory for storing data which may be written on, and data read from, a length of magnetic tape. Circuitry, including a microprocessor, DMA controller and service requests, handles data transfer between a host and the tape via the cache memory so that delays due to tape accelerations and decelerations are masked and the host can instantaneously read data bi-directionally and instantaneously switch between read and write operations.