Abstract: A data base management system of a data processing system handles a hierarchical structure model. Matrix type data, considered as having different hierarchical structure in accordance with the application, is effectively handled by storing in the form of one-dimensional data in a file device and making up the desired hierarchical structure when used. This is accomplished by providing first order address information and designating a scheme code which defines the desired hierarchical structure when the data is utilized by a user.

Abstract: A pipelined Fast Fourier Transform (FFT) processor is described for proceng continuous sets of N samples in a highly efficient manner. Within a single set of N inputs, the samples arrive in pairs (sample 0, and 1, 2 and 3, 4 and 5, etc.). This input sequence can be obtained from a sequential stream of inputs (sample 0 followed by smples 1, 2, 3, 4, etc.) by delaying the even numbered sample by one time unit. Alternately, the device could be made to operate on sequential samples within a set of N samples by internal pipelining of the arithmetic units. The device achieves high arithmetic unit efficiency while minimizing the memory required by allowing each arithmetic unit in the pipeline, with the exception of the last, to operate on the even or odd numbered samples first, after which it will operate on the remaining samples, which have been appropriately delayed and switched through shift registers and switches.

Abstract: A microprogram control system of the invention has a mapping read only memory storing the respective initial addresses of a plurality of microprogram routines corresponding to a macroinstruction. The address input information to this mapping read only memory is obtained from an output of a binary counter which counts every time a JUMP instruction for making a branch to another microprogram routine is decoded, and from an output of a latch circuit for holding the operation code of the macroinstruction. When the microprogram routine has loops, a count inhibit signal is input to the binary counter so that the same address input information may be supplied to the mapping read only memory.