Abstract: In an integrated circuit, a multiplexor receives incoming data at a first rate and is controllable by a high rate clock signal to output that data serially at a second, higher rate. A processing device receives the data from the multiplexor at the higher rate and is controllable by a high rate clock signal to process that data. Clock generation circuitry receives a first clock signal at the first rate and produces the high rate signal for the processing device and the multiplexor. Clock generation circuitry includes sequentially connected delay devices, one connected to receive the first clock signal. Each delay device produces a trigger signal and an output signal a predetermined time after receiving the trigger signal from the previous delay device. A control circuit is common to the delay devices for controlling the predetermined time interval. An output circuit receives the output signals of the delay devices and produces the high rate clock signal.

Abstract: In a communications network comprising two counterflowing busses (folded bus or dual bus) and a number of stations (N1, N2, N3) connected between them, a cyclic reservation and access technique is provided. A headend unit generates consecutive time slots for data transmission which are grouped in cycles. For each cycle, the headend first issues a reservation command (RES) with a cycle number and a reservation count which each station augments by the slot count required locally. Each station stores the cycle number with the requested slot count. The headend stores in a global reservation queue, for each returning reservation command, the cycle number and the accumulated reservation count. Later it issues a start command (ST) with the respective cycle number, and subsequently generates the required number of slots as indicated by the stored accumulated reservation count. The headend can issue additional confirm commands and reject commands for activating a backpressure mechanism.

Abstract: A communication system provides high speed transmission of data over a link, such as a fiber optic link, between a first terminal and a second terminal. The architecture and protocol permits the use of dedicated hardware such as state machines constructed of programmable array logic units, to synchronize the transmission and reception of data packets and the retransmission of designated ones of these packets in the event of a faulty transmission. Packets to be transmitted and received are stored in an array of frames in sub-windows of a memory storage window in each of the termianls, the frame number being equal to the sequence number of the data packet.