Patents Examined by Menatoallah Youssef
  • Patent number: 11496120
    Abstract: A flip-flop with glitch protection is disclosed. The flip-flop includes a differential amplifier circuit that generates amplifier output signals based on an input data and clock signals and precharges a true data node when a clock signal is inactive. A latch circuit is coupled to the differential amplifier and includes a latch node. Responsive to a current value of the input data signal having a first logic state, the latch node is set at a logic value equivalent to the precharged value during an active phase of the clock signal. Responsive to the current value of the input data signal having a second logic state complementary to the first, during the active phase of the clock signal, the latch circuit causes the latch node to be set to a logic value complementary to the precharged value, using the clock signal and the current value of the input data signal.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: November 8, 2022
    Assignee: Apple Inc.
    Inventors: Qi Ye, Ajay Bhatia, Vivekanandan Venugopal
  • Patent number: 11480988
    Abstract: A device for controlling a first voltage with a second voltage includes a first terminal of application of the second voltage and a second terminal for supplying the first voltage. A comparator has a first input terminal connected to the first terminal and has a second input terminal receiving information representative of the first voltage. At least one first current source of programmable intensity is connected to the second input terminal of the comparator.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: October 25, 2022
    Assignee: STMicroelectronics (Alps) SAS
    Inventor: Patrik Arno
  • Patent number: 11476846
    Abstract: According to one embodiment, a drive control circuit includes a first transistor that supplies a current to a gate of an output transistor in response to a drive signal, a second transistor that supplies a current to a capacitor in response to the drive signal, a comparison circuit that compares a gate voltage of the output transistor and a voltage of the capacitor, a control signal generation circuit that generates a control signal in response to an output signal of the comparison circuit and the drive signal, and a third transistor that supplies a current to a gate of the output transistor in response to the control signal.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: October 18, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yuichi Sawahara, Hideaki Majima
  • Patent number: 11476748
    Abstract: A method for controlling a resonance type power converter including a first resonance circuit (L0, C0) and a shunt circuit (3), which converts and outputs the power of the DC power supply, shunting a current flowing into a first capacitor (CS) by controlling a second switching element (S2) during a predetermined period within turn-off period of a first switching element (S1), the first capacitor connected in parallel to the first switching element (S1), the second switching element (S2) included in the shunt circuit (3), and the first switching element (S1) operated in response to the resonance of the first resonance circuit (L0, C0).
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: October 18, 2022
    Assignee: NISSAN MOTOR CO., LTD.
    Inventors: Toshihiro Kai, Kousuke Saito, Shigeharu Yamagami, Keisuke Inoue, Kraisorn Throngnumchai
  • Patent number: 11476776
    Abstract: A voltage-controlled delay buffer includes a plurality of inverters configured in a cascade topology to receive an input signal from a source circuit and output an output signal to an output circuit. The plurality of inverters includes a voltage-controlled inverter controlled by a control signal having a first voltage and a second voltage. The voltage-controlled inverter includes a PMOS transistor configured to assist a low-to-high transition of an outgoing signal, and an NMOS transistor configured to assist a high-to-low transition of the outgoing signal. Two varactors, one forward connected and the other backward connected are configured to adjust a delay of a transition of an incoming signal. Another two varactors, one forward connected and the other backward connected, configured to adjust a delay of a transition of the outgoing signal in accordance with the first voltage and the second voltage.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: October 18, 2022
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Chia-Liang (Leon) Lin
  • Patent number: 11469741
    Abstract: The driver circuit includes a pull-up network having a first pull-up transistor controlled by a data signal, a second pull-up transistor coupled between the first pull-up transistor and a first power supply voltage, and a third pull-up transistor coupled in parallel with the second pull-up transistor. The third pull-up transistor is configured to turn on for at least one clock cycle responsive to a change in the logic level of the data signal being detected.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: October 11, 2022
    Assignee: Synopsys, Inc.
    Inventors: Eliyahu Dan Zamir, Michael William Kawa Lynch, Davit Petrosyan
  • Patent number: 11469757
    Abstract: Systems, methods, techniques and apparatuses of power switches are disclosed. One exemplary embodiment is a power switch comprising a first semiconductor device and a second semiconductor device coupled together in a first anti-series configuration between a first terminal and a second terminal; a third semiconductor device and a fourth semiconductor device coupled together in a second anti-series configuration between the first terminal and the second terminal; a controller configured to operate the power switch to simultaneously conduct a first portion of a load current from the first terminal to the second terminal by closing the first semiconductor device and the second semiconductor device, and to conduct a second portion of the load current from the first terminal to the second terminal by closing the third semiconductor device and the fourth semiconductor device.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: October 11, 2022
    Assignee: ABB SCHWEIZ AG
    Inventors: Pietro Cairoli, Eddy Aeloiza, Xiaoqing Song
  • Patent number: 11463086
    Abstract: A circuit comprises an H-bridge circuit that includes a pair of current sources and a plurality of transistors. The H-bridge circuit includes a first output and a second output. One of the current sources is coupled to receive a supply voltage. A control circuit is configured to control, based on a sum of voltages on the first and second outputs, current of at least one of the current sources through at least some of the plurality of transistors.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: October 4, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Kannan Krishna
  • Patent number: 11444617
    Abstract: A set and reset pulse generator circuit receives an input signal to generate a set signal and a reset signal pair. The set and reset pulse generator circuit includes a set circuit and a reset circuit. A cross-coupling circuit connects a voltage signal of the reset circuit to an output circuit of the set circuit, and another cross-coupling circuit connects a voltage signal of the set circuit to an output circuit of the reset circuit. The output circuit of the set circuit generates the set signal from the input signal, the voltage signal of the reset circuit, and the voltage signal of the set circuit. The output circuit of the reset circuit generates the reset signal from an inverted input signal, the voltage signal of the reset circuit, and the voltage signal of the set circuit.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: September 13, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Kyoung Min Lee, Kaitlyn Sitch
  • Patent number: 11418176
    Abstract: A multi-frequency uniformization carrier wave slope random distribution pulse width modulation method, includes: (1) selecting a required random carrier wave sequence and a modulating wave, and after the two are compared, generating a switch device drive signal for pulse width modulation; (2) determining a multiple n of an equivalent carrier frequency f of the random carrier wave sequence, and selecting a main circuit topology; and (3) inputting the switch device drive signal generated in (1) into the main circuit topology of (2) to perform multi-frequency uniformization carrier wave slope random distribution pulse width modulation. The disclosure can improve a frequency domain distribution bandwidth of a harmonic wave without changing the mean and variance of a random carrier wave sequence, and realizes uniform distribution of carrier waves and multiple harmonic peaks near a doubled frequency of the carrier waves in a wider frequency domain.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: August 16, 2022
    Assignee: NAVAL UNIVERSITY OF ENGINEERING
    Inventors: Jie Xu, Ziling Nie, Junjie Zhu, Tinghao Wu, Weiwei Ye, Yi Han, Xingfa Sun, Wenkai Xu, Jingxin Yuan
  • Patent number: 11404869
    Abstract: A system for distributing DC bus voltage and control power to multiple motors includes a rectifier front end supplying a DC bus voltage and a DC control voltage. Both the DC bus voltage and the DC, control voltage are distributed via a common set of conductors. Diodes are operatively connected between the DC control voltage and the common set of conductors. The diodes allow forward conduction of the DC control voltage and distribution of control power to distributed devices when the DC bus voltage is not present. Once the DC bus voltage is present, the diodes block conduction of the DC control voltage. Each of the distributed devices are configured with an internal power supply that is operative to generate an internal control voltage from either the DC control voltage or the DC bus voltage.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: August 2, 2022
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Zoran Vrankovic, Mark A. Gries, Craig R. Winterhalter, Arun K. Guru
  • Patent number: 11394383
    Abstract: A switch comprising: a channel path comprising first and second MOS transistors with common source and gate terminals and drain terminals defining first and second terminals of the channel path; and control circuitry comprising: a third MOS transistor comprising: a gate coupled to the common source terminal; a source coupled to the common gate terminal by a resistor; and a drain coupled to a first reference terminal; a first current source coupled between the first reference terminal and the common gate terminal for providing a first current; a second current source coupled between the source terminal of the third MOS transistor and a second reference terminal for providing a second current greater than the first current; and a first switching arrangement configured to selectively enable and disable the first current source; and a second switching arrangement configured to selectively couple the common source terminal to the second reference terminal.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: July 19, 2022
    Assignee: NXP USA, Inc.
    Inventors: Hongwei Liu, Olivier Tico, Stephan Ollitrault
  • Patent number: 11394379
    Abstract: Disclosed herein is a switch device including a switch element coupled between a power supply terminal and an output terminal, and an output abnormality detection circuit that. When an output current flowing during a turn-on period of the switch element is smaller than a threshold value, the output abnormality detection circuit detects an occurrence of an output abnormal condition, and increases a turn-on resistance of the switch element to determine which of a load-open condition and a short-to-power-supply-voltage condition is occurring at the output terminal on a basis of an output voltage at the output terminal.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: July 19, 2022
    Assignee: ROHM Co., LTD.
    Inventor: Toru Takuma
  • Patent number: 11378600
    Abstract: A circuit is disclosed. The circuit includes an input port, an output port, a squelch detector and a disconnect detector. The squelch detector and the disconnect detector are enabled or disabled by a signal such that only one of the squelch detector and the disconnect detector is active at a given time. When the squelch detector is active, a threshold generator generates a squelch threshold for the squelch detector based on a squelch configuration data indicative of a predefined squelch threshold. When the disconnect detector is active, the threshold generator generates a disconnect threshold for the disconnect detector based on a disconnect configuration data indicative of a predefined disconnect threshold.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: July 5, 2022
    Assignee: NXP B.V.
    Inventors: Siamak Delshadpour, Ranjeet Kumar Gupta, Xu Zhang
  • Patent number: 11361241
    Abstract: Methods, systems, and apparatus for determining frequencies at which to operate interacting qubits arranged as a two dimensional grid in a quantum device. In one aspect, a method includes the actions of defining a first cost function that characterizes technical operating characteristics of the system. The cost function maps qubit operation frequency values to a cost corresponding to an operating state of the quantum device; applying one or more constraints to the defined first cost function to define an adjusted cost function; and adjusting qubit operation frequency values to vary the cost according to the adjusted cost function such that the operating state of the quantum device is improved.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: June 14, 2022
    Assignee: Google LLC
    Inventors: Paul Klimov, Julian Shaw Kelly
  • Patent number: 11354481
    Abstract: A phase shifter includes an active region, a first and a second set of gates and a set of contacts. The active region extends in a first direction and is located at a first level. The first and second set of gates each extend in a second direction, overlap the active region and are located at a second level. The second set of gates are positioned along opposite edges of the active region, are configured to receive a first voltage, and are part of a first transistor. The first transistor is configured to adjust a first capacitance of the phase shifter responsive to the first voltage. The set of contacts extend in the second direction, are over the active region, are located at a third level, and are positioned between at least the second set of gates.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: June 7, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Hsien Lin, Ho-Hsiang Chen, Hsien-Yuan Liao, Tzu-Jin Yeh, Ying-Ta Lu
  • Patent number: 11329643
    Abstract: A driver circuit controls an output unit that switches whether or not to supply a current to an output line, in accordance with a potential difference between a first control signal to be input and a voltage of the output line. The driver circuit has a control line transmitting the first control signal to the output unit; a connection switching unit switching whether or not to connect the control line and the output line; a pre-stage control unit that is provided between a high potential line and a low potential line and selects and outputs a potential of any one of the high potential line and the low potential line in accordance with a second control signal; and a post-stage control unit causing the connection switching unit to connect the control line and the output line when the pre-stage control unit outputs a voltage higher than a predetermined threshold value.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: May 10, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Morio Iwamizu
  • Patent number: 11321627
    Abstract: A fault tolerant quantum computer is implemented using hybrid acoustic-electric qubits. A control circuit includes an asymmetrically threaded superconducting quantum interference devices (ATS) that excites excite phonons in a mechanical resonator by driving a storage mode of the mechanical resonator and dissipates phonons from the mechanical resonator via an open transmission line coupled to the control circuit, wherein the open transmission line is configured to absorb photons from a dump mode of the control circuit.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: May 3, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Patricio Arrangoiz Arriola, Amir Safavi-Naeini, Oskar Jon Painter, Connor Hann, Fernando Brandao, Kyungjoo Noh, Joseph Kramer Iverson, Harald Esko Jakob Putterman, Christopher Chamberland, Earl Campbell
  • Patent number: 11316420
    Abstract: A circuit includes first and second transistors, an adaptive bias current source circuit, and an adaptive resistance circuit. The first transistor has a control terminal and first and second current terminals. The control terminal of the first transistor being a first input to the circuit. The second transistor has a control terminal and first and second current terminals, and the control terminal of the second transistor is a second input to the circuit. The first and second inputs are differential inputs to the circuit. The adaptive bias current source circuit is coupled to the second current terminal of the first transistor. The adaptive resistance circuit is coupled between the second current terminal of the second transistor and the adaptive bias current source circuit.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: April 26, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rohit Phogat, Ramakrishna Ankamreddi, Isha Agrawal
  • Patent number: 11316504
    Abstract: To make it possible to use a transistor with relatively low gate withstand voltage at an output stage in an apparatus including a differential amplifier. An apparatus is provided. The apparatus includes: a differential amplifier having a first current path and a second current path that form a differential pair; a first output-stage transistor that has: a first main terminal connected on a power-supply potential side; a second main terminal connected on a reference-potential side; and a control terminal connected to the second current path; and a first voltage-clamp circuit connected between the control terminal and second main terminal of the first output-stage transistor.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: April 26, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tetsuya Kawashima