Patents Examined by Menghyao Zhe
  • Patent number: 8544008
    Abstract: A data processing system is provided with at least one processing unit (1) for an interleaved processing of multiple tasks (T1-T3), and a cache (5) associated to the at least one processing unit (1) for caching data for the multiple tasks (T1-T3) to be processed by the at least one processing unit (1). The cache (5) is divided into a plurality of cache lines (6). Each of the cache lines (6) is associated to one of the multiple tasks (T1-T3). Furthermore, a task scheduler (10) is provided for scheduling the multiple tasks (T1-T3) to be processed in an interleaved manner by the at least one processing unit (1). A cache controller (20) is provided for selecting those cache lines (6) in the cache (5), which are to be evicted from the cache (5). This selection is performed based on the task scheduling of the task scheduler (10).
    Type: Grant
    Filed: December 5, 2005
    Date of Patent: September 24, 2013
    Assignee: NXP B.V.
    Inventors: Sainath Karlapalem, Bijo Thomas, Nagaraju Bussa