Abstract: A computer architecture for providing enhanced reliability by coupling a plurality of commonly shared busses called streets with a plurality of smart switching elements called HUBs. The streets are bi-directional busses for transferring data between HUB elements. The HUB elements are capable of directing data across the street structures to the desired destination. The HUB elements have a built in priority scheme for allowing high priority data to be transferred before low priority data. The either increase or decrease the number of HUB elements and streets can be.
Type:
Grant
Filed:
December 23, 1993
Date of Patent:
February 27, 1996
Assignee:
Unisys Corporation
Inventors:
Donald W. Mackenthun, Larry L. Byers, Gregory B. Wiedenman, Ferris T. Price, deceased
Abstract: An apparatus and method for scheduling a sequence of instructions for achieving multiple launches and multiple executions of the instructions within a central processing unit. Each of the instructions is classified according to which one of multiple execution resources of the central processing unit executes the instruction. The classifications include memory reference operations, integer operations, program control operations, and floating point arithmetic operations. The classifications associated with the instructions occur in the order in which the instructions occur in the sequence.
Type:
Grant
Filed:
March 7, 1994
Date of Patent:
January 30, 1996
Assignee:
Ross Technology, Inc.
Inventors:
Anantakotiraju Vegesna, Jayachandra B. Avula, Peter H. Jewett, Yatin G. Mundkur