Abstract: A secret information protection system for protecting secret information stored in an information processing system from access by an unauthorized user after an authorized user terminates the authorized user's use of the information processing system. The secret information protection system includes a storage device for storing the secret information and an erasure instructing device for generating an erasing instruction to erase the secret information from the storage device. The erasure instructing device has a switch, operated by the authorized person when the authorized person terminates the authorized person's use of the information processing system, for generating the erasing instruction when the authorized person terminates the authorized person's use of the information processing system. An erasure device erases the secret information in accordance with the erasing instruction from the erasure instructing device.

Abstract: An information processing system has a main memory unit, an expanded memory unit, and an instruction processing unit producing a virtual address. An address translation table, namely, a page table stores page table words which include main/expanded memory presence bits indicating to which memory unit of the main memory unit and the expanded memory unit real pages are stored. Preferably, the instruction processing unit may include an access type determiner for determining an access type for at least one operand. The access type indicates which memory unit is the optimum one for the operand. Instead of the access type determiner, the instruction processing unit may include segment descriptor registers for storing segment descriptors having expanded memory bits indicating which memory units are the optimum ones for the segments.

Abstract: A memory access scheme achieved using a memory address register and a register-indirect memory accessing mode eliminates write back collisions, long cycle time, and enhances system performance. During memory address generation operations, an arithmetic-logic unit (ALU) generates memory addresses from data in a general purpose register (GPR). Then, the memory addresses are written back to the GPR and a memory address register (MAR). During memory access operations, the MAR is accessed for the memory addresses to access a memory. Two approaches are provided. In a first approach, use of the MAR during the memory access operations is explicit. In a second approach, use of the MAR during the memory access operations is transparent. According to the second approach, a controller is provided to validate the MAR during the memory access operations.

Abstract: A virtual machine system in which a plurality of operating systems (OS's) can run on one computer including a physical main storage (physical MS), and at least one physical extended storage (physical ES), each operating system (OS) of the OS's having a virtual MS on the physical MS and at least one virtual ES on the at least one physical ES.

Abstract: A novel nonvolatile memory element or cell comprising a memory means consisting of at least one superconducting ring (21, 22) and a detector means consisting of a MOSFET. The superconducting ring and the MOSFET are arranged in such a manner that a magnetic flux created by the superconducting ring (21, 22) passes through a channel zone of the MOSFET. Information is held in the superconducting ring in a form of permanent current and is detected electrically as variation in the conductivity of the channel zone of the MOSFET.

Abstract: Virtual address space for array data to be stored in a virtual memory is allocated by establishing a table that associates segments of the virtual address space with predetermined array data dimensions and maintaining a map that identifies, for each segment, which portions of the segment have been allocated to store array data. The table and map are used to identify a contiguous portion of the virtual address space for the array data to be stored.

Abstract: A signal margin testing system is provided for a memory having a word line voltage boosting circuit which uses a test mode decode circuit to selectively disable the word line boosting circuit and then read out data from storage cells in the memory.

Abstract: A hardware system provides a programmable method for addressing expanded memory specification (EMS) registers in a personal computing system functioning with an MS-Dos.RTM. operating system or the like. The system provides hardware flexibility for addressing EMS registers at different addresses than the standard LIM EMS specification calls for, to permit utilization of register addresses in otherwise unavailable locations. The address translations are effected through hardware; so that no additional delays in the circuit operation occur.

Abstract: A dual port static memory cell with one cycle read-modify-write operation. The static memory cell includes a write line for receiving new data to be written into the static memory cell, switching means for coupling the new data into the static memory cell, and an extended word line generator for generating an extended word line signal. The extended word line signal controls the switching means. During the active state of the extended word line signal, the switching means is enabled to couple new data into the static memory cell while precharge is placed on a bit line coupled to the static memory cell, without disturbing the precharge. The extended word line signal goes active in response to an active state of the word line signal and remains active even after the word line signal goes inactive. The extended word line signal returns to an inactive state prior to the beginning of a new memory cycle. The inactive state of the extended word line signal decouples the new data from the switching means.

Abstract: This dynamic random access memory having a plurality of rated voltages as an operation supply voltage operates accurately with a sufficient operating margin for each rated voltage. The dynamic random access memory comprises a circuit (220; 120, 130) for generating a signal for defining operation speed/timing of a sense amplifier (50) depending on the operation supply voltage, and a circuit (210) for driving the sense amplifier in response to an output of a defining signal generating circuit. The sense amplifier driving circuit comprises a first gate (G1) for transmitting a sense amplifier activating signal as it is in response to the defining signal, a second gate (G2) for passing therethrough a sense amplifier activating signal passed through a delay circuit (100) in response to the defining signal, and transistors (25, 25'; 25) for driving the sense amplifier in response to outputs of the first and second gates. One of the first and second gates is activated by the defining signal.

Abstract: The method and apparatus for using the memory in an information processing system of the virtual addressing type is characterized in that a first memory domain DX is organized around a logical address of NX bits in size. In the memory domain DX, a plurality of address spaces EAX of identical structure is defined and relative addressing of a size NL less than NX is allowed. One of the address spaces EAX (hereinafter the current address space EAC) is assigned temporarily and interchangeably to a second memory domain DL organized around an address that is NL bits in size.

Abstract: A nonvolatile memory system for one of a multiple of values includes a memory cell having an input terminal, an output terminal, and a control terminal. The memory cell, which may be an EEPROM, stores nonvolatile electric charge, and establishes a voltage threshold between the input terminal and the output terminal which influences a current therebetween, the threshold having a level which is dependent upon the amount of the electric charge stored by the storing means. A writing circuit is connected to the input terminal and is responsive to an input data signal having a value selected from among at least three values for applying electric charge, in an amount corresponding to the value of the selected data signal, to the input terminal for storage in the memory cell. A reading circuit is provided to measure the value of the voltage threshold between the input and output terminals and to output a data signal having a value which corresponds to the measured value of the threshold voltage.

Abstract: A refresh control circuit for a processor which is connected to dynamic random access memory via an address bus, a data bus and control signal lines. A refresh control signal is output at predetermined intervals to refresh the dynamic random access memory. The refresh control circuit includes control circuitry and an address generator. The address generator latches a value received from the control circuitry. Based on such latched value, a refresh address is changed by the N-th power of 2, N corresponding to the number of memory banks of the dynamic random access memory.

Abstract: A semiconductor memory device includes a plurality of memory cells each having a bipolar transistor whose collector-emitter voltage V.sub.CE is controlled according to the base potential to satisfy the condition of I.sub.BE <I.sub.CB when the forward base current in the base-emitter path and the reverse base current in the collector-base path are respectively expressed by I.sub.BE and I.sub.CB and a switching element connected to the bipolar transistor, word lines, bit lines and emitter electrode lines connected to the memory cells, and functions as a dynamic memory cell in the data storing operation and as a gain memory cell in the readout operation.

Abstract: A multifunctional memory comprises a mask ROM (2). When an "L" level signal is applied to a control pin (EXT), data is read out from the ROM (2) in response to an address signal inputted from a multiplex pin (AD/DA). Thereafter, the data read out from the ROM (2) is outputted from the multiplex pin (AD/DA). In this case, an "H" level signal is outputted from a chip select pin (CS). When an "H" level signal is applied to the control pin (EXT), an "L" level signal is outputted from the chip select pin (CE). Consequently, the EPROM (30) is rendered active. In addition, the address signal inputted from the multiplex pin (AD/DA) is outputted from a port/address pin (PORT/AD). Data is read out from the EPROM (30) in response to the address signal.