Patents Examined by Michael Ayers
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Patent number: 9952885Abstract: Some embodiments provide a method for an application operating on a host machine. The method receives a configuration of a Dynamic Host Configuration Protocol (DHCP) service for implementation within a virtualized container on the host machine. The configuration includes several database table entries. The method converts the several database table entries into a configuration file for use by a process that operates in the virtualized container. the method initializes the process in the virtualized container. The process in the virtualized container reads the configuration file in order to perform DHCP services for machines connected to at least one logical forwarding element of a logical network.Type: GrantFiled: October 31, 2013Date of Patent: April 24, 2018Assignee: NICIRA, INC.Inventors: Anupam Chanda, Pankaj Thakkar, Igor Ganichev, Ronghua Zhang, Ansis Atteka
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Patent number: 9880883Abstract: To provide a virtual resource control system capable of appropriately defining the amounts of allocated virtual resources to individual service systems under an environment in which service systems are added or deleted. A resource excessive/lacking amount calculation means 54 simulates a resource consumption situation of each node in the service system by use of a hybrid model, and calculates the amount of excessive/lacking resource indicating the lacking amount or the excessive amount of the amount of allocated virtual resource corresponding to one entire service system corresponding to a service management device. The resource excessive/lacking amount calculation means 54 notifies the amount of excessive/lacking resource to a hub device 60, and receives a notification of the new amount of allocated virtual resource corresponding to the entire service system. A notification by the resource excessive/lacking amount calculation means 54 and a response from the hub device 60 are made asynchronously.Type: GrantFiled: June 24, 2014Date of Patent: January 30, 2018Assignee: NEC CorporationInventor: Seiichi Koizumi
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Patent number: 9875136Abstract: A novel approach to coordinate processes in a process environment includes establishing a coherent temporal and resource framework for operation of selected processes in order to formulate a basis for coordination. A key aspect of the present innovation includes the novel techniques for coordinating processes including transmission of electromagnetism and transmission of electromagnetic radiation in a process environment by effecting periodic interruptions, based upon the abovementioned coherent temporal and resource framework, while maintaining the required operational and safety procedures.Type: GrantFiled: May 11, 2013Date of Patent: January 23, 2018Inventors: Indrajith Kuruppu, Don Damith Nadishan Colambathanthrige
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Patent number: 9870265Abstract: Systems and methods for prioritizing cloud-based computing tasks are provided. An example method includes, identifying a first plurality of service requests submitted by a plurality of users including a first user; selecting a first service request, in the plurality of service requests, in accordance with a first priority, where the first service request is submitted by the first user; selecting a second service request submitted by the first user, in a second plurality of service requests submitted by the first user, in accordance with a second priority, where the second service request is associated with a first job type; and selecting a third service request submitted by the first user, in a third plurality of service requests submitted the first user, in accordance with a third priority, where the third plurality of service requests submitted the first user are associate with a same job type.Type: GrantFiled: December 9, 2014Date of Patent: January 16, 2018Assignee: SUCCESSFACTORS, INC.Inventors: Mao Geng, Yukching Leung, Ming Zhang, Fan Wang
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Patent number: 9804871Abstract: A processing core comprising instruction execution logic circuitry and register space. The register space to be loaded from a VMCS, commensurate with a VM entry, with information indicating whether a service provided by the processing core on behalf of the VMM is enabled. The instruction execution logic to, in response to guest software invoking an instruction: refer to the register space to confirm that the service has been enabled, and, refer to second register space or memory space to fetch input parameters for said service written by said guest software.Type: GrantFiled: March 15, 2013Date of Patent: October 31, 2017Assignee: Intel CorporationInventors: Gilbert Neiger, Barry E. Huntley, Ravi L. Sahita, Vedvyas Shanbhogue, Jason W. Brandt
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Patent number: 9804870Abstract: A processing core comprising instruction execution logic circuitry and register space. The register space to be loaded from a VMCS, commensurate with a VM entry, with information indicating whether a service provided by the processing core on behalf of the VMM is enabled. The instruction execution logic to, in response to guest software invoking an instruction: refer to the register space to confirm that the service has been enabled, and, refer to second register space or memory space to fetch input parameters for said service written by said guest software.Type: GrantFiled: September 27, 2012Date of Patent: October 31, 2017Assignee: Intel CorporationInventors: Gilbert Neiger, Barry E. Huntley, Ravi L. Sahita, Vedvyas Shanbhogue, Jason W. Brandt
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Patent number: 9766926Abstract: A method for executing a program in parallel includes creating a program replica, which includes a write operation on and an identifier of an object and is a copy of the program, for a thread. The identifier specifies whether the object is thread-local. The method includes modifying the write operation based on a speculation that the write operation uses only thread-local objects. The write operation executes in a transaction of the thread. The method includes determining, while executing the program replica and using the identifier, that the object used by the write operation is not thread-local, de-optimizing the write operation by adding instrumentation to implement a software transactional memory (STM) system for the write operation to obtain a de-optimized write operation, and performing the de-optimized write operation on the object to obtain a result and store the result in a redo log.Type: GrantFiled: January 31, 2014Date of Patent: September 19, 2017Assignee: Oracle International CorporationInventors: Daniele Bonetta, Thomas Wuerthinger
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Patent number: 9753779Abstract: A plurality of tasks are processed simultaneously in a plurality of CPUs. A task control circuit is connected to the plurality of CPUs, and when executing a system call signal instruction, each CPU transmits a system call signal to the task control circuit. Upon receipt of a system call signal from a CPU 0, the task control circuit 200 refers to a processor management register, identifies a RUN-task of the CPU 0, selects a READY-task that is to be executed next, switches process data of the RUN-task and process data of the READY-task, and updates processor management information.Type: GrantFiled: November 17, 2014Date of Patent: September 5, 2017Assignee: Renesas Electronics CorporationInventor: Naotaka Maruyama
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Patent number: 9740563Abstract: Controlling a software process by causing the execution of a first software process on a computer, where the first software process is configured to exclusively access a resource on the computer, causing the execution of a second software process on the computer when the first software process has exclusive access to the resource, where the second software process is configured to perform a first predefined action that is independent of the second software process accessing the resource, attempt to access the resource, and perform a second predefined action that is dependent on the second software process accessing resource, and causing the first software process to terminate its exclusive access to the resource, thereby causing the second software process to access the resource and perform the second predefined action.Type: GrantFiled: May 24, 2013Date of Patent: August 22, 2017Assignee: International Business Machines CorporationInventors: Mandeep Kaur Jandir, Limor Provizor, Mark L. Yakushev, Asaf Yeger
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Networking stack of virtualization software configured to support latency sensitive virtual machines
Patent number: 9703589Abstract: A host computer has a plurality of containers including a first container executing therein, where the host also includes a physical network interface controller (NIC). A packet handling interrupt is detected upon receipt of a first data packet associated with the first container If the first virtual machine is latency sensitive, then the packet handling interrupt is processed. If the first virtual machine is not latency sensitive, then the first data packet is queued and processing of the packet handling interrupt is delayed.Type: GrantFiled: August 25, 2014Date of Patent: July 11, 2017Assignee: VMware, Inc.Inventors: Haoqiang Zheng, Lenin Singaravelu, Shilpi Agarwal, Daniel Michael Hecht, Garrett Smith -
Patent number: 9697031Abstract: A method for implementing an inter-virtual processor interrupt is provided, which includes: when a source virtual processor needs to trigger an interrupt to a target virtual processor, writing register data that includes information about the target virtual processor and indication data used to indicate that the source virtual processor triggers the interrupt to the target virtual processor into a virtual register of a virtual advanced programmable interrupt controller (vAPIC) of the source virtual processor, so that a virtual machine monitor obtains the information about the target virtual processor and the indication data from the virtual register by means of parsing, and the virtual machine monitor injects an inter-virtual processor interrupt into the target virtual processor according to the information about the target virtual processor and the indication data.Type: GrantFiled: November 24, 2014Date of Patent: July 4, 2017Assignee: Huawei Technologies Co., Ltd.Inventors: Hongyong Zang, Haoyu Zhang
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Patent number: 9690633Abstract: A synchronization method of multiple threads is executed by a computer. The synchronization method includes determining a type of a synchronization process of a first thread performing the synchronization process for synchronization with a second thread; starting time measurement when the type of the synchronization process of the first thread is a first type; performing the synchronization process of the first thread and a synchronization process of the second thread based on a synchronization process history of the second thread when the measured time exceeds a permitted response period of the first thread; and updating the permitted response period and performing the synchronization processes of the first thread and the second thread based on the synchronization process history of the second thread, when another processing request is received.Type: GrantFiled: June 13, 2013Date of Patent: June 27, 2017Assignee: FUJITSU LIMITEDInventors: Koji Kurihara, Koichiro Yamashita, Takahisa Suzuki, Hiromasa Yamauchi, Toshiya Otomo
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Patent number: 9672073Abstract: Distributing work in a distributed computing environment that includes multiple nodes. An individual node can receive a work assignment, which can then be divided into a plurality of work units. A first work unit can then be distributed to a first worker node. At least a portion of the first work unit can be re-distributed to a second worker node in response to determining that the first worker node has experienced a failure condition with respect to the first work unit.Type: GrantFiled: June 7, 2012Date of Patent: June 6, 2017Assignee: SYBASE, INC.Inventors: Kurt Wilhelm Deschler, Kaushal Mittal, Curtis Grant Johnson, Victor Mesenzeff, Jr., William Harrison Cox
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Patent number: 9665579Abstract: Computing a date and time format includes obtaining a UT value of a reference time; computing intermediate data including year, month, day, hour, minute, and second, from the UT value of the reference time; computing a difference between a conversion target UT value and the UT value of the reference time using a processor; computing values of hour, minute, and second, based on the difference between the UT values; and generating a character string format representing year, month, day, hour, minute, and second, by combining the intermediate data and the values of hour, minute, and second.Type: GrantFiled: October 1, 2013Date of Patent: May 30, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Toshiaki Yasue
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Patent number: 9658887Abstract: A single workload scheduler schedules sessions and tasks having a tree structure to resources, wherein the single workload scheduler has scheduling control of the resources and the tasks of the parent-child workload sessions and tasks. The single workload scheduler receives a request to schedule a child session created by a scheduled parent task that when executed results in a child task; the scheduled parent task is dependent on a result of the child task. The single workload scheduler receives a message from the scheduled parent task yielding a resource based on the resource not being used by the scheduled parent task, schedules tasks to backfill the resource, and returns the resource yielded by the scheduled parent task to the scheduled parent task based on receiving a resume request from the scheduled parent task or determining dependencies of the scheduled parent task have been met.Type: GrantFiled: September 23, 2015Date of Patent: May 23, 2017Assignee: International Business Machines CorporationInventors: Alicia E. Chin, Yonggang Hu, Zhenhua Hu, Jason T S Lam, Zhimin Lin
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Patent number: 9652299Abstract: A hardware thread causes a SleepID register of a WAKEUP signal generation unit to store a SleepID that identifies the hardware thread when suspending a process due to waiting for a process by another CPU. The WAKEUP signal generation unit causes the WAKEUP data register of the WAKEUP signal generation unit to store a SleepID notified by a node when a process that the hardware thread waits ends. The WAKEUP signal generation unit outputs a WAKEUP signal that cancels the stop of the hardware thread to the hardware thread when the SleepIDs of the SleepID register and the WAKEUP data register agree with each other.Type: GrantFiled: October 17, 2012Date of Patent: May 16, 2017Assignee: FUJITSU LIMITEDInventors: Hideyuki Koinuma, Hideyuki Kizawa, Keiji Miyauchi
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Patent number: 9646011Abstract: Computing a date and time format includes obtaining a UT value of a reference time; computing intermediate data including year, month, day, hour, minute, and second, from the UT value of the reference time; computing a difference between a conversion target UT value and the UT value of the reference time using a processor; computing values of hour, minute, and second, based on the difference between the UT values; and generating a character string format representing year, month, day, hour, minute, and second, by combining the intermediate data and the values of hour, minute, and second.Type: GrantFiled: September 5, 2013Date of Patent: May 9, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Toshiaki Yasue
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Patent number: 9558023Abstract: Provided are techniques for comparing a first fileset associated with a first operating system (OS) with a second fileset associated with a second OS; determining, based upon the comparing, that the second OS is a more current version of the first OS; in response to the determining that the second OS is a more current version of the first OS, moving, in conjunction with live application mobility, a virtual machine (VM) workload partition (WPAR) on the first LPAR to a second LPAR, the moving comprising determining a set of overlays associated with the WPAR corresponding to the second OS; removing from the WPAR any overlays associated with the first OS; applying to the WPAR a set of overlays corresponding to the second OS; check pointing processes associated with the WAPR; and copying live data associated with the LPAR from the first LPAR to the second LPAR.Type: GrantFiled: November 12, 2013Date of Patent: January 31, 2017Assignee: International Business Machines CorporationInventors: Frederic Barrat, Christine M. Briand, Laurent Dufour, Khalid Filali-Adib, Perinkulam I. Ganesh, J. Mark McConaughy, Stephen B. Peckham, David W. Sheffield, Marc J. Stephenson, Nathaniel S. Tomsic, Sungjin Yook
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Patent number: 9535765Abstract: A global-level manager access a work order from a client and parameters associated with the work order. A service level agreement to meet the work order parameters is determined. The service level agreement includes a price. An indication is received from the client that the service level agreement is accepted. The one or more input files are partitioned into multiple shards, and the work order into multiple jobs. The jobs are distributed among a plurality of clusters to be processed using underutilized computing resources in the clusters. The job outputs are combined to form the work order output. The jobs are monitored to insure that the deadline for completion of the work order will be met.Type: GrantFiled: March 28, 2012Date of Patent: January 3, 2017Assignee: Google Inc.Inventors: David Konerding, Jordan M. Breckenridge, Daniel Belov
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Patent number: 9535729Abstract: Provided are techniques for comparing a first fileset associated with a first operating system (OS) with a second fileset associated with a second OS; determining, based upon the comparing, that the second OS is a more current version of the first OS; in response to the determining that the second OS is a more current version of the first OS, moving, in conjunction with live application mobility, a virtual machine (VM) workload partition (WPAR) on the first LPAR to a second LPAR, the moving comprising determining a set of overlays associated with the WPAR corresponding to the second OS; removing from the WPAR any overlays associated with the first OS; applying to the WPAR a set of overlays corresponding to the second OS; check pointing processes associated with the WPAR; and copying live data associated with the LPAR from the first LPAR to the second LPAR.Type: GrantFiled: May 1, 2013Date of Patent: January 3, 2017Assignee: International Business Machines CorporationInventors: Frederic Barrat, Christine M. Briand, Laurent Dufour, Khalid Filali-Adib, Perinkulam I. Ganesh, J. Mark McConaughy, Stephen B. Peckham, David W. Sheffield, Marc J. Stephenson, Nathaniel S. Tomsic, Sungjin Yook