Patents Examined by Michael C Maskulinski
  • Patent number: 7437618
    Abstract: A method, apparatus, and computer program product are disclosed in a processor for dynamically, during runtime, allocating memory for in-memory hardware tracing. The processor is included within a data processing system. The processor includes multiple processing units that are coupled together utilizing a system bus. The processing units include a memory controller that controls a system memory. A particular size of the system memory is determined that is needed for storing trace data. A hardware trace facility requests, dynamically after the data processing system has completed booting, the particular size of the system memory to be allocated to the hardware trace facility for storing trace data that is captured by the hardware trace facility. The firmware selects particular locations within the system memory. All of the particular locations together are the particular size. The firmware allocates the particular locations for use exclusively by the hardware trace facility.
    Type: Grant
    Filed: February 11, 2005
    Date of Patent: October 14, 2008
    Assignee: International Business Machines Corporation
    Inventors: Ra'ed Mohammad Al-Omari, Alexander Erik Mericas, William John Starke
  • Patent number: 7437617
    Abstract: A method, apparatus, and computer program product are disclosed for, in a processor, concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers. A hardware trace facility captures hardware trace data in a processor. The hardware trace facility is included within the processor. The hardware trace data is transmitted to a system memory utilizing a system bus. The system memory is included within the system. The system bus is capable of being utilized by processing units included in the processing node while the hardware trace data is being transmitted to the system bus. Part of system memory is utilized to store the trace data. The system memory is capable of being accessed by processing units in the processing node other than the hardware trace facility while part of the system memory is being utilized to store the trace data.
    Type: Grant
    Filed: February 11, 2005
    Date of Patent: October 14, 2008
    Assignee: International Business Machines Corporation
    Inventors: Ra'ed Mohammad Al-Omari, Alexander Erik Mericas, William John Starke
  • Patent number: 7437614
    Abstract: The present disclosure provides for affording synchronization in an automated scripting framework. First, script data is received utilizing a language-driven interface. Then, reports having user readable sentences are created based on the received script data. The received script data is then translated into automation code. Finally, automated testing is provided utilizing the automation code.
    Type: Grant
    Filed: April 13, 2005
    Date of Patent: October 14, 2008
    Assignee: Accenture LLP
    Inventors: John Jeffrey Haswell, Robert J. Young, Kevin Schramm
  • Patent number: 7437615
    Abstract: A storage system includes at least one storage medium, at least one controller to control the storage medium, and a communication path to connect the storage medium and the controller in a loop for communication between the controller and the storage medium, wherein a failure diagnosis is performed to locate a failure while performing normal read/write operations.
    Type: Grant
    Filed: May 17, 2005
    Date of Patent: October 14, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Koji Iwamitsu, Kenji Oonabe
  • Patent number: 7434105
    Abstract: A system for selective self-healing of memory errors comprises a processor coupled to a memory, where the memory stores instructions executable by the processor to store an error record for each memory management error detected during an execution of the application. The error record identifies an allocation location (e.g., a portion of a stack trace corresponding to the invocation of a memory allocation function such as malloc( )) of an object associated with the memory management error. The instructions are executable to use the error record to identify, during subsequent execution, memory operations performed on objects allocated from the allocation location, and to perform corresponding memory protection operations (e.g., operations to prevent re-occurrences of the memory errors) for the memory operations identified using the error record.
    Type: Grant
    Filed: November 7, 2005
    Date of Patent: October 7, 2008
    Assignee: Symantec Operating Corporation
    Inventors: Gustavo Rodriguez-Rivera, Michael P. Spertus
  • Patent number: 7434089
    Abstract: A system and process for loading control software into the control panel of a liquid chiller system is provided. A PCMCIA card socket is installed on a circuit board of a liquid chiller control system and is in direct connection with microprocessor data and address buses. A linear flash PCMCIA card having new control software for the control panel is inserted into the PCMCIA card socket when the control panel is de-energized. The control software from the PCMCIA card is loaded into a flash memory of the control system by software executed directly from the PCMCIA card. The software in the PCMCIA card erases the flash memory of the control system, copies the control software from the PCMCIA card to the flash memory and then confirms that the copy of the control software was successful. After the control software has been copied, the control panel is de-energized, the PCMCIA card is removed and the chiller system is restarted and executes the new control software stored in the flash memory.
    Type: Grant
    Filed: August 12, 2004
    Date of Patent: October 7, 2008
    Assignee: York International Corporation
    Inventors: Bart Andrew Smith, Jeffrey Daniel Boyer
  • Patent number: 7426662
    Abstract: A manager transmits an I/O bus signal to an I/O bus manager in a computer at a predetermined point of time to inform the I/O bus manager of occurrence of an I/O bus fault. The I/O bus manager initializes an I/O bus and then informs a CPU in the computer of the I/O bus fault as an interruption to be processed by an OS operated by the CPU, whereby the OS can acquire the fault information after the interruption even in the case where an I/O bus fault occurs.
    Type: Grant
    Filed: March 14, 2005
    Date of Patent: September 16, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Tomoki Sekiguchi, Toshiaki Arai, Hiroshi Furukawa, Kazumi Ikeda
  • Patent number: 7424647
    Abstract: A system and a method for transferring data in an emission-monitoring system from a first computer to a second computer are provided. The method includes generating a first message containing a first software variable having a first site-specific value that is transmitted from the first computer to the second computer. The first site-specific value is indicative of whether one of a fault event, a maintenance event, or a calibration event associated with the first computer has occurred. The method further includes receiving the first message at the second computer, the second computer storing the first site-specific value in a first record of a first database. The first record is associated with the first software variable. The method further includes determining whether the first site-specific value indicates that an event has occurred.
    Type: Grant
    Filed: July 19, 2004
    Date of Patent: September 9, 2008
    Assignee: General Electric Company
    Inventors: Neil Colin Widmer, Rekha Anil
  • Patent number: 7424640
    Abstract: An apparatus and method for a computer system is used for implementing an extended distributed recovery block fault tolerance scheme. The computer system includes a supervisory node, an active node and a standby node. Each of the nodes has a primary routine, an alternate routine and an acceptance test for testing the output of the routines. Each node also includes a device driver, a monitor and a node manager for determining the operational configuration of the node. The supervisory node coordinates the operation of the active and standby nodes. The primary and alternate routines are implemented with an application task through a plurality of agent objects operating as finite state machines. A reliable data link extends between the monitors of the active and standby nodes.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: September 9, 2008
    Assignee: Harris Corporation
    Inventor: Andy E. Rostron
  • Patent number: 7421617
    Abstract: A system and method is provided for optimizing restoration of stored data. A request for data to be restored to any point in time is received. A current state of the data is determined. One or more data blocks required to modify the data from the current state to the any point in time requested are identified. The data at the any point in time is restored within a storage medium using the identified one or more data blocks.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: September 2, 2008
    Assignee: Symantec Corporation
    Inventors: Curtis Anderson, John P. Woychowski, Pratik Wadher
  • Patent number: 7412632
    Abstract: A method and system to facilitate failure modes and effects analysis (FMEA) of one or more components of a system. The FMEA is indicated with the generation of an FMEA form. A graphical user interface provides a sequential order of completion for a number of steps. The steps are followed to generate graphical representations which are to be completed by an FMEA analyst and received by the graphical user interface to facilitate generating the FMEA form.
    Type: Grant
    Filed: November 25, 2003
    Date of Patent: August 12, 2008
    Assignee: Ford Motor Company
    Inventors: Richard Liddy, Bruce Maeroff, David Craig, Toni Brockers, Uwe Oettershagen, Tim Davis
  • Patent number: 7412626
    Abstract: A method and system for handling errors and exceptions in an ERP environment are disclosed. According to one aspect of the present invention, a condition or event causes a script-engine associated with a particular ERP server to generate an error message. The error message is communicated to a centralized controller-node. The centralized controller-node analyzes the message and determines the best course of action for handling an error or exception related to the error message. Based on the controller node's analysis, the controller node communicates a response message, thereby enabling the process that caused the error to continue without terminating abnormally.
    Type: Grant
    Filed: May 21, 2004
    Date of Patent: August 12, 2008
    Assignee: SAP AG
    Inventors: Eric Wood, Boris Tsyganskiy
  • Patent number: 7409592
    Abstract: An exemplary embodiment of the invention relates to a system for facilitating coverage feedback testcase generation reproducibility. The system comprises a domain definition input file for defining a coverage domain element and an internal coverage domain data store in communication with the domain definition input file. The internal coverage domain data store stores domain definitions collected from the domain definition input file as well as updates made to the coverage domain element. The system also includes a test case generator in communication with the internal coverage domain data store. The test case generator generates testcases. The system also includes a pseudo-random generated seed assigned to a successfully generated testcase. The successfully generated testcase is replicated without generating each prior testcase utilizing the pseudo-random generated seed. The replication includes an initial coverage state for the successfully generated testcase.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: August 5, 2008
    Assignee: International Business Machines Corporation
    Inventor: Mark H. Decker
  • Patent number: 7409582
    Abstract: A storage subsystem such as an array of disk drives, method of managing disk drives in the storage subsystem and program product therefor. The storage subsystem may be a redundant array of independent disks (RAID) and the individual disks drives may be Self-Monitoring, Analysis and Reporting Technology (SMART) capable drives. When one of the drives gives an indication of an impending failure, a disk image of the failing disk is built on an available spare disk. Once the image is complete, the failing disk may be replaced without down time for rebuilding a failed disk.
    Type: Grant
    Filed: May 6, 2004
    Date of Patent: August 5, 2008
    Assignee: International Business Machines Corporation
    Inventors: Andrew B. McNeill, Jr., Thomas H. Newsom
  • Patent number: 7404105
    Abstract: A method and system are provided for enabling replacement of a failed processor without requiring redundancy of hardware. The system is a multiprocessing computer system that includes one or more processor chips. Each processor chip may include one or more logical processors. During system initialization, one or more logical processors may be reserved in an inactive state. In the event an error is detected on a logical or physical processor, one or more reserved logical processors may have execution context transferred from the processor experiencing the error. Thereafter, the active processor is designated as inactive and replaced by the inactive processor to which the execution context has been transferred.
    Type: Grant
    Filed: August 16, 2004
    Date of Patent: July 22, 2008
    Assignee: International Business Machines Corporation
    Inventor: Susumu Arai
  • Patent number: 7404101
    Abstract: A method for determining an optimal configuration and redundancy allocation for a system containing a plurality of units grouped into a plurality of elements and one or more modules. The method conducts random statistical sampling of a combinatorial space reflecting the possible combinations, redundancies and integrations of the units and elements in a given system. For each sample combination, the method calculates an optimization metric that reflects the reliability and/or the cost of that combination. The optimization metric may incorporate relative weighting of constraints used to evaluate whether the combination is optimal. The optimum configuration will be the configuration having the lowest optimization metric out of all the samples.
    Type: Grant
    Filed: November 4, 2003
    Date of Patent: July 22, 2008
    Assignee: Lucent Technologies Inc.
    Inventors: Stacy G. Fishkin, Gopal N. Kumar
  • Patent number: 7392420
    Abstract: A system, method and article of manufacture are provided for the automatic recovery from errors encountered during an automated Licensed Internal Code (LIC) update on a storage controller. The present invention functions with a concurrent or nonconcurrent automated LIC update. The automated recovery from many error conditions is transparent to the attached host system and on-site service personnel, resulting in an improvement in the LIC update process.
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: June 24, 2008
    Assignee: International Business Machines Corporation
    Inventors: Edward George Butt, Jack Harvey Derenburger, Steven Douglas Johnson, Vernon J. Legvold, Ronald David Martens
  • Patent number: 7389446
    Abstract: A method for reducing soft error rates in semiconductor memory. In one embodiment, memory is partitioned into a) boot and download memory, b) program memory and c) data memory. Each partition receives protection according to the importance of the data stored. The boot memory is protected by sensing errors and repairing them utilizing on-chip data storage redundancy and exchange. The program memory is protected by sensing errors and repairing damaged data by reloading it using the program stored in the boot and download memory. The data memory is selectively protected similar to the program memory, but with the added feature of regular saving to disk from which to check for accurate data in the event of corruption. In another embodiment, any or all of the soft error protection features are selectable on a global basis, a memory type basis or, in the cases of program and data memory, on a block level basis.
    Type: Grant
    Filed: August 16, 2004
    Date of Patent: June 17, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: Keith Krasnansky
  • Patent number: 7380175
    Abstract: A method of operating a supercomputer having N computing elements each connected to a fast communications link is disclosed, the method comprising the steps of: operating the supercomputer to perform a computing operation; upon failure of a fast communications link transferring state from a computing element which, as a result of the fast communications link failure, is no longer able to communicate, to a spare computing element not previously engaged in the computing operation, and continuing the computing operation with the spare computing element, wherein the number of redundant elements M is chosen to satisfy the expression BM[N, (1?PT)]>S where S is a desired probability of successful completion of the computing operation within a time T and P is the probability of successful operation per unit time of a fast communications link.
    Type: Grant
    Filed: April 12, 2005
    Date of Patent: May 27, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Richard Taylor, Christopher Tofts
  • Patent number: 7343527
    Abstract: A method and system for detecting and managing an error detected in an iSCSI (Internet Small Computer System Interface) PDU (Protocol Data Unit) by using a RDMA (Remote Direct Memory Access) dedicated receive error queue for error recovery.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: March 11, 2008
    Assignee: International Business Machines Corporation
    Inventors: Vadim Makhervaks, Giora Biran, Zorik Machulsky, Kalman Zvi Meth, Renato J. Recio