Abstract: A random data generation system having a transceiver and a processor is disclosed. The transceiver receives user defined attributes via a user interface of a user device. The user defined attributes include configuration information and workload information associated with a workload model. The configuration information includes information associated with an external system. The workload information includes information associated with a random data to be transmitted to the external system, and a first frequency at which the random data is to be transmitted during peak time duration and a second frequency at which the random data is to be transmitted during non-peak time duration. The processor may render the user interface, and obtain the user defined attributes. The processor may generate the random data, and transmit the random data to the external system based on the user defined attributes.

Abstract: A processing-in-memory (PIM) device includes memory banks, first and second global buffers, multiplying-and-accumulating (MAC) operators, and output circuits. Each memory bank includes a left memory bank providing left weigh data and a right memory bank providing right weigh data. The first global buffer provides left vector data, and the second global buffer provides right vector data. Each MAC operator includes a left MAC operator performing a MAC operation on the left weight data and the left vector data to generate left MAC data and a right MAC operator performing a MAC operation on the right weight data and the right vector data to generate right MAC data. Each output circuit adds the left MAC data to the right MAC data to generate MAC result data and outputs the MAC result data or activation function-processed MAC result data in response to first and second MAC read signals.

Abstract: A system including digital oscillators and at least one programmable interconnect is described. The programmable interconnect(s) provide weights for and selectably couples at least a portion of the digital oscillators. The digital oscillators and the programmable interconnect(s) form an optimization processing unit (OPU). A system for performing reversible logic is also described. The system includes digital oscillators coupled to perform a logic operation and an error correction unit coupled to the digital oscillators. The error correction unit is configured to sample states of the digital oscillators, detect error(s) in the states, and tune connection coefficient(s) between the oscillators in response to detecting the error(s).

Abstract: A processing-in-memory device includes a data storage region and an arithmetic circuit. The data storage region includes a first memory bank in which first data is divided into a first portion and a second portion and stored, and a second memory bank in which second data is divided into a first portion and a second portion and stored. The arithmetic circuit performs multiplication/accumulation operations on the first data and the second data and outputs final MAC result data.

Abstract: A data processing device includes: an input data determining unit configured to determine whether or not each of binarized input data is a predetermined value; a storage unit configured to store a plurality of coefficients and coefficient address information including information related to coefficient addresses where the plurality of coefficients are stored; a control unit configured to read the coefficient address from the storage unit based on a determination result of the input data determining unit and read the coefficient from the storage unit based on the coefficient address; and an arithmetic unit configured to execute an arithmetic operation related to the coefficient acquired by the control unit.

Abstract: A computer processing system and method for computing large-degree isogenies having a computer processor resident on an electronic computing device operably configured to execute computer-readable instructions programmed to perform a large-degree isogeny operation by chaining together a plurality of scalar point multiplications, a plurality of isogeny computations, and a plurality of isogeny evaluations.

Abstract: Provided is a method and system for performing multi-device-based inference for a large language model. A multi-device-based inference performance system may include a plurality of devices configured to map to partitions that separate a large language model (LLM) according to an intra-layer parallelism method. Here, each of the plurality of devices may be implemented to synchronize data by sharing a sub-result of matrix multiplication on the data with another device of the plurality of devices while the matrix multiplication is being performed.

Abstract: Disclosed is a method and apparatus with deep learning operations. A deep learning apparatus includes a processor, configured to support a plurality of different operation modes, including a systolic array having a plurality of multiplier accumulator (MAC) units, and a control circuit configured to respectively control, for each the plurality of different operation modes, select operations of the plurality of MAC units and data movements among the plurality of MAC units.

Abstract: A secure multiparty computation method permits the computation of an arithmetic function ƒ which can be expressed as the addition of A groups of multiplications of a set S of private input secrets {s0, s1, . . . , sS-1}. Dealer nodes holding the secrets are provided with a base blinding factor ?a whose inverse is the sum of a set of pseudorandom numbers each of which is associated with a respective computing node and is not shared with other computing nodes. Each dealer node is further provided with an exponent blinding factor ?a,m specific to the secret being contributed, where all of the exponent blinding factors sum to unity. The dealer nodes share with the computing nodes the product of the secrets with the base blinding factor raised to the exponent blinding factor. Each computing nodes can independently and without sharing computations, generate from the product of shares it receives from the dealer nodes a result share. Summing the result shares provides the result of the computation.

Abstract: A system and method for performing sets of multiplications in a manner that accommodates outlier values. In some embodiments the method includes: forming a first set of products, each product of the first set of products being a product of a first activation value and a respective weight of a first plurality of weights. The forming of the first set of products may include multiplying, in a first multiplier, the first activation value and a least significant sub-word of a first weight to form a first partial product; multiplying, in a second multiplier, the first activation value and a least significant sub-word of a second weight; multiplying, in a third multiplier, the first activation value and a most significant sub-word of the first weight to form a second partial product; and adding the first partial product and the second partial product.

Abstract: Disclosed are systems and methods for performing efficient vector-matrix multiplication using a sparsely-connected conductance matrix and analog mixed signal (AMS) techniques. Metal electrodes are sparsely connected using coaxial nanowires. Each electrode can be used as an input/output node or neuron in a neural network layer. Neural network synapses are created by random connections provided by coaxial nanowires. A subset of the metal electrodes can be used to receive a vector of input voltages and the complementary subset of the metal electrodes can be used to read output currents. The output currents are the result of vector-matrix multiplication of the vector of input voltages with the sparsely-connected matrix of conductances.

Abstract: A processing element for implementation in a digital signal processing system is provided. The processing element is configured to receive a first data stream comprising a plurality of digital values where each value represents a sample of an analog signal. The processing element is further configured to receive a second data stream comprising a series of digital values where each value represents a sample of the analog signal. The processing element is configured to filter the first data stream via a first Farrow-structured fractional delay (FD) filter and output a filtered first data stream; filter the second data stream via a second Farrow-structured FD filter and output a filtered second data stream; and temporarily store values from the second data stream and output the stored values to the first Farrow-structured FD filter so that the stored values can be used to filter the first data stream.

Abstract: A decimal floating-point instruction is executed in a round-for-reround mode. The decimal floating-point instruction is configured to perform a decimal floating-point operation on a decimal floating-point operand. The executing includes forming based on performing the decimal floating-point operation, an intermediate result having a high order portion and a low order portion. The high order portion has a least significant digit. A rounded-for-reround number is created from the intermediate result. The rounded-for-reround number includes the high order portion of the intermediate result and based on the least significant coefficient digit of the high order portion being a selected value and based on the low order portion having another selected value, the least significant digit of the rounded-for-reround number is incremented. The rounded-for-reround number is stored.

Abstract: A matrix multiplication engine can include a plurality of processing elements configured to compute a matrix dot product as a summation of a sequence of vector-vector outer-products.

Abstract: According to one implementation of the present disclosure, a method includes performing a spatial alignment of at least one of first or second data tiers of a circuit; and performing a computation based on the spatial alignment of the at least one of the first and second data tiers. According to another implementation of the present disclosure, a circuit includes: a compute circuitry; and at least first and second data tiers of two or more data tiers positioned at least partially overlapping one another. In an example, each of the at least first and second data tiers is coupled to the compute circuitry. In certain implementations, the positioning of the first and second data tiers at least partially overlapping one another corresponds to a spatial alignment.

Abstract: A computer processing system that includes at least one arithmetic logic unit in a computer processing device and includes at least one addition circuit operably configured to compute addition operations, operably configured to receive two numerical inputs, and operably configured to compute a sum and includes at least one modular multiplication circuit operably configured to receive the sum from the at least one addition circuit, receive at least one other numerical input, and receive a numerical modulus to perform a modular multiplication operation and generate a modular multiplication operation result.

Abstract: A random number generator system is disclosed that includes a quantum event source for generating a quantum event, a quantum event detector for detecting the generated quantum event, a clock circuit providing a looping counting signal including a plurality of counts (n0, n1 etc.), a converter circuit for associating the detected quantum event with a contemporaneous count of the plurality of counts, and a processing system for providing a random number based on the contemporaneous count.

Abstract: Photonic processors are described. The photonic processors described herein are configured to perform matrix multiplications (e.g., matrix vector multiplications). Matrix multiplications are broken down in scalar multiplications and scalar additions. Some embodiments relate to devices for performing scalar additions in the optical domain. One optical adder, for example, includes an interferometer having a plurality of phase shifters and a coherent detector. Leveraging the high-speed characteristics of these optical adders, some processors are sufficiently fast to support clocks in the tens of gigahertz of frequency, which represent a significant improvement over conventional electronic processors.

Abstract: Circuitry for decomposing block floating-point numbers into lower precision floating-point numbers is provided. The circuitry may include a high precision storage circuit configured to provide high precision floating-point numbers, input selectors configured to receive the high precision floating-point numbers from the high precision storage circuit and to generate corresponding lower precision floating-point components with adjusted exponents, and a low precision block floating-point vector circuit configured to combine the various lower precision floating-point components generated by the input selectors. The lower precision floating-point components may be processed spatially or over multiple iterations over time.

Abstract: Integrated circuits with dot product circuitry are provided. The dot product circuitry may be configured to generate partial products of different ranks based on the inputs. The partial products may be organized into corresponding groups based on their ranks. Each group of partial products having the same rank can then be compressed using a compressor/reduction tree. At least some of the compressed partial product values may be shifted between the different groups to maintain the proper offset. Each partial product may have an associated one's to two's complement conversion bit. The conversion bits of the various partial product groups can be separately aggregated and then injected into the compressor tree at one or more locations.