Abstract: A method for performing a fundamental computational primitive in a device is provided, where the device includes a processor and a matrix multiplication accelerator (MMA). The method includes configuring a streaming engine in the device to stream data for the fundamental computational primitive from memory, configuring the MMA to format the data, and executing the fundamental computational primitive by the device.

Abstract: The invention relates to devices for generating true random numbers, comprising a digital chaotically oscillating autonomous Boolean network as a source of entropy. According to the invention, the proposed digital chaotically oscillating autonomous Boolean network consists in three logic elements connected to each other, two of which represent two-input “Exclusive OR” and/or “Exclusive NOR” gates, and the third logic element has three inputs and one output, and implements a logic “counting ones” function, in which its output is set to a logic one if a logic one is present at no more than one of its inputs, otherwise it is set to a logic zero. The achieved technical result consists in an increase in true random number generation rate while decreasing energy consumption.

Abstract: Various aspects relate to a multiply and accumulate circuit, the multiply and accumulate circuit including: a plurality of multiply operation cells configured in a matrix arrangement. A respective multiply operation cell of the multiply operation cells includes: a field-effect transistor and a programmable switch in a series connection, wherein the field-effect transistor and the programmable switch are configured to control a current flow through the respective multiply operation cell to realize a multiplication operation. The multiply operation cells of a set of the plurality of multiply operation cells share a corresponding control line to realize an accumulation operation in addition to the multiply operations carried out by the set of multiply operation cells.

Abstract: An apparatus is described. The apparatus includes a long short term memory (LSTM) circuit having a multiply accumulate circuit (MAC). The MAC circuit has circuitry to rely on a stored product term rather than explicitly perform a multiplication operation to determine the product term if an accumulation of differences between consecutive, preceding input values has not reached a threshold.

Abstract: A system and method include forecasting a series of future data points in a long sequence time series data using a decoder-only transformer model by dividing the long sequence time series data into a plurality of sequences, converting each sequence of the plurality of sequences into a first vector to obtain a plurality of first vectors, creating a plurality of second vectors from the time stamps associated with the plurality of data points, combining the first vector with the second vector of each sequence of the plurality of sequences to obtain a plurality of third vectors, computing a context matrix from the plurality of third vectors, performing a convolution operation on the context matrix to forecast the series of future data points, and outputting the series of future data points from the prediction layer.

Abstract: The present disclosure provides a data analysis apparatus including a time series analysis state memory unit configured to store a state of a time series data analysis; a time series analysis unit configured to analyze input data points belonging to time series data generated by a plurality of data sources and update the state stored the time series analysis state memory unit; and a filtering apparatus including: a data fetching unit configured to fetch data points from the data sources; a quality target memory unit; and a data point selection optimization unit configured to select data points based on a quality target stored in the quality target memory unit and data input from the time series analysis state memory unit.

Abstract: To reduce power consumption, data bits or a portion of a data register that is not expected to toggle frequently can be grouped together, and be clock-gated independently from the rest of the data register. The grouping of the data bits can be determined based on the data types of the workload being operated on. For a data register configured to store a numeric value that supports multiple data types, the portion of the data register being clock-gated may store a group of data bits that are unused for one or more data types of the multiple data types supported by the data register. The portion of the data register being clock-gated can also be a group of data bits that remain unchanged or have a constant value for numeric values within a certain numeric range that is frequently operated on.

Abstract: Methods, apparatuses, and systems for in-or near-memory processing are described. Strings of bits (e.g., vectors) may be fetched and processed in logic of a memory device without involving a separate processing unit. Operations (e.g., arithmetic operations) may be performed on numbers stored in a bit-parallel way during a single sequence of clock cycles. Arithmetic may thus be performed in a single pass as numbers are bits of two or more strings of bits are fetched and without intermediate storage of the numbers. Vectors may be fetched (e.g., identified, transmitted, received) from one or more bit lines. Registers of a memory array may be used to write (e.g., store or temporarily store) results or ancillary bits (e.g., carry bits or carry flags) that facilitate arithmetic operations. Circuitry near, adjacent, or under the memory array may employ XOR or AND (or other) logic to fetch, organize, or operate on the data.

Abstract: Provided are an integrated circuit chip apparatus and a related product, the integrated circuit chip apparatus being used for executing a multiplication operation, a convolution operation or a training operation of a neural network. The present technical solution has the advantages of a small amount of calculation and low power consumption.

Abstract: A computation unit includes input lines to provide a floating-point value, a first lookup table, a second lookup table, a range detector, and an output stage. The input lines include exponent lines and mantissa lines. The first lookup table has a first address input coupled to a first subset of the input lines to provide a first output. The second lookup table has a second address input coupled to a second subset of the input lines to provide a second output. The range detector is coupled to at least some of the input lines and indicates whether the floating-point value provided on the input lines is within a specified range on a range output. The output stage is operatively coupled to the first output, the second output and the range output, to generate a function output based on the first output, the second output, and the range output.

Abstract: A processor, a method of operating the processor, and an electronic device including the processor are disclosed. The method includes arranging, in respective input registers, weights and activations having a smaller number of bits than a minimum operation unit of an operator included in the processor, performing a multiplication between values stored in the input registers, storing a result of the multiplication in an output register, and outputting, from the output register, a value in a preset bit range as a result of a dot product between a first vector including the weights and a second vector including the activations.

Abstract: Techniques for neural network processing using specialized data representation are disclosed. Input data for manipulation in a layer of a neural network is obtained. The input data includes image data, where the image data is represented in bfloat16 format without loss of precision. The manipulation of the input data is performed on a processor that supports single-precision operations. The input data is converted to a 16-bit reduced floating-point representation, where the reduced floating-point representation comprises an alternative single-precision data representation mode. The input data is manipulated with one or more 16-bit reduced floating-point data elements. The manipulation includes a multiply and add-accumulate operation. The manipulation further includes a unary operation, a binary operation, or a conversion operation. A result of the manipulating is forwarded to a next layer of the neural network.

Abstract: The present disclosure describes a method for conditioning and preprocessing raw cosmic ray data to extract features and generate a binary string representing the inherent randomness in the data. Measurable characteristics of cosmic ray particles, such as arrival times and amplitudes, are processed to create random binary sequences. These binary strings are then used to train a generative adversarial network (GAN) framework. In the GAN framework, the generator creates random sequences resembling the target distribution, which matches the entropy of the conditioned cosmic data. The discriminator evaluates the generated sequences by comparing them to the conditioned cosmic data and assigns a randomness score that characterizes the quality of the generated sequences. This adversarial process ensures the generation of high-quality random sequences that are statistically indistinguishable from the conditioned input data.

Abstract: A neural network operation apparatus includes an input register to store an input feature map, a processing element array including a processing element to perform an operation based on the input feature map and a weight matrix, and a controller to map a portion of the input feature map and a portion of the weight matrix, both on which the operation is to be performed, to the processing element.

Abstract: Classical computer systems can generate certified random bit strings using an untrusted quantum computer. The classical computer system can issue a sequence of challenges to the quantum computer, with each challenge involving execution of an apparently-random quantum circuit generated by the classical client. By executing the quantum circuits, the quantum computer can generate a high-entropy bit sequence, and the classical client can use the high-entropy bit sequence to generate sequences of random bits. The classical client can use models of quantum probability distributions for at least some of the challenges to verify that the bit sequence was generated by a quantum computer executing the quantum circuit generated by the classical client, thereby supporting certification of the randomness of the sequence of bits.

Abstract: A processor or other device, such as a programmable and/or massively parallel processor or other device, includes processing elements designed to perform arithmetic operations (possibly but not necessarily including, for example, one or more of addition, multiplication, subtraction, and division) on numerical values of low precision but high dynamic range (“LPHDR arithmetic”). Such a processor or other device may, for example, be implemented on a single chip. Whether or not implemented on a single chip, the number of LPHDR arithmetic elements in the processor or other device in certain embodiments of the present invention significantly exceeds (e.g., by at least 20 more than three times) the number of arithmetic elements, if any, in the processor or other device which are designed to perform high dynamic range arithmetic of traditional precision (such as 32 bit or 64 bit floating point arithmetic).

Abstract: Some embodiments provide an IC for implementing a machine-trained network with multiple layers. The IC includes a set of circuits to compute a dot product of (i) a first number of input values computed by other circuits of the IC and (ii) a set of predefined weight values, several of which are zero, with a weight value for each of the input values. The set of circuits includes (i) a dot product computation circuit to compute the dot product based on a second number of inputs and (ii) for each input value, at least two sets of wires for providing the input value to at least two of the dot product computation circuit inputs. The second number is less than the first number. Each input value with a corresponding weight value that is not equal to zero is provided to a different one of the dot product computation circuit inputs.

Abstract: A method to implement a fixed-point scale layer in a neural network for data processing is provided in the present disclosure. The method includes: receiving fixed-point input data over a channel of a standalone floating-point scale layer, and converting the floating-point input data into fixed-point input data of the standalone floating-point scale layer; obtaining fixed-point quantization parameters in each channel based on the input data and floating-point parameters ?i, ?i in each channel; converting the standalone floating-point scale layer based on the fixed-point quantization parameters into a fixed-point scale layer for processing the fixed-point input data to generate fixed-point output data; and mapping the fixed-point scale layer to a fixed-point convolution layer and the computation of convolution is done by matrix multiplication that can be executed on a GEMM engine.

Abstract: A matrix multiplication hardware architecture is provided, including: a reduction network, including a tree topology with multiple levels formed by a plurality of reduction network nodes, where the reduction network node includes a data selector and two computation paths; and a digital signal processing unit DSP48 chain, formed by cascading a plurality of digital signal processing units DSP48, where output ends of adjacent digital signal processing units DSP48 are respectively connected to two computation paths of a same reduction network node in a first level of the tree topology, and outputs of two computation paths pass through a data selector and then are connected to a reduction network nodes in an upper level of the tree topology.

Abstract: An apparatus for applying dynamic quantization of a neural network is described herein. The apparatus includes a scaling unit and a quantizing unit. The scaling unit is to calculate an initial desired scale factors of a plurality of inputs, weights and a bias and apply the input scale factor to a summation node. Also, the scaling unit is to determine a scale factor for a multiplication node based on the desired scale factors of the inputs and select a scale factor for an activation function and an output node. The quantizing unit is to dynamically requantize the neural network by traversing a graph of the neural network.