Patents Examined by Michael D Yaary
  • Patent number: 10929213
    Abstract: In an approach for protecting recoding logic in a computing environment, a processor obtains an operand of an instruction in a first data format. A processor converts the operand from the first data format to a second data format. A processor generates a predicted residue of the operand in the second data format, wherein generating the predicted residue of the operand in the second data format comprises: generating a residue of the operand from the first data format.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: February 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Carlough, Petra Leber, Daniel Lipetz, Silvia M. Mueller
  • Patent number: 10929764
    Abstract: An apparatus includes a state machine engine. The state machine engine may also include an automaton, whereby the automaton is configured to analyze data from a beginning of an input data stream until a point when an end of data signal is seen. The automaton may further be configured to report an event representative of a satisfaction of a Boolean clause of a conjunctive normal form (CNF) Boolean expression representative of a Boolean Satisfiability problem (SAT) by a portion of the input data stream.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: February 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Matthew T. Grimm, Jeffery M. Tanner
  • Patent number: 10915385
    Abstract: In an approach for protecting recoding logic in a computing environment, a processor obtains an operand of an instruction in a first data format. A processor converts the operand from the first data format to a second data format. A processor generates a predicted residue of the operand in the second data format, wherein generating the predicted residue of the operand in the second data format comprises: generating a residue of the operand from the first data format.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: February 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Carlough, Petra Leber, Daniel Lipetz, Silvia M. Mueller
  • Patent number: 10902087
    Abstract: A processing device is provided which includes memory and a processor comprising a plurality of processor cores in communication with each other via first and second hierarchical communication links. Each processor core in a group of the processor cores is in communication with each other via the first hierarchical communication links. Each processor core is configured to store, in the memory, one of a plurality of sub-portions of data of a first matrix, store, in the memory, one of a plurality of sub-portions of data of a second matrix, determine an outer product of the sub-portion of data of the first matrix and the sub-portion of data of the second matrix, receive, from another processor core of the group of processor cores, another sub-portion of data of the second matrix and determine another outer product of the sub-portion of data of the first matrix and the other sub-portion of data of the second matrix.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: January 26, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Shaizeen Aga, Nuwan Jayasena, Allen H. Rush, Michael Ignatowski
  • Patent number: 10891256
    Abstract: A vector memory subsystem for use with a programmable mix-radix vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values. In an exemplary embodiment, an apparatus includes a vector memory bank and a vector memory system (VMS) that generates input memory addresses that are used to store input data into the vector memory bank. The VMS also generates output memory addresses that are used to unload vector data from the memory banks. The input memory addresses are used to shuffle the input data in the memory bank based on a radix factorization associated with an N-point DFT, and the output memory addresses are used to unload the vector data from the memory bank to compute radix factors of the radix factorization.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: January 12, 2021
    Assignee: Cavium, LLC
    Inventors: Yuanbin Guo, Hong Jik Kim
  • Patent number: 10891108
    Abstract: A calculation device includes: M coefficient storage units provided corresponding to the M coefficients, each of the M coefficient storage units including a positive-side coefficient and a negative-side coefficient representing a coefficient corresponding to a sign of a difference; M multiplication units provided corresponding to the M input values, each of the M multiplication units calculating a positive-side multiply value obtained by multiplying the positive-side coefficient included in the corresponding coefficient storage unit by a sign inverted according to the corresponding input value and a negative-side multiply value obtained by multiplying the negative-side coefficient included in the corresponding coefficient storage unit by a sign inverted according to the corresponding input value; and an output unit outputting an value according to a difference between a positive-side sum value obtained by summing the M positive-side multiplication values and a negative-side sum value obtained by summing the M
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: January 12, 2021
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takao Marukame, Yoshifumi Nishi, Kumiko Nomura
  • Patent number: 10885147
    Abstract: A first evaluation function calculation unit and a second evaluation function calculation unit calculate a cost function term Ei and a penalty function term Pi in an evaluation function, respectively. A transition control unit stochastically determines whether to accept any of state transitions, based on a product of a ratio between an inverse temperature ?i and a penalty factor ?i and Pi and Ei. An exchange control unit supplies ?i and ?i to each annealing unit, ?i and ?i having been set such that each annealing unit has a different ratio between ?i and ?i, receives Ei and Pi from each annealing unit, and exchanges ?i between first and second annealing units among the plurality of annealing units and ?i between the first and second annealing units, in accordance with a probability based on ?i, ?i, Ei, and Pi of the first and second annealing units.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: January 5, 2021
    Assignee: FUJITSU LIMITED
    Inventor: Motomu Takatsu
  • Patent number: 10877729
    Abstract: Systems and methods that provide reconfigurable shifter configurations supporting multiple instruction, multiple data (MIMD) are described. Shifters implemented according to embodiments support multiple data shifts with respect to an instance of data shifting, wherein multiple individual different data shifts are implemented at a time in parallel. Reconfigurable segmented scalable shifters of embodiments, in addition being reconfigurable for scalability in supporting data shifting with respect to various bit lengths of data, are configured to support data shifting of differing bit lengths in parallel. The data shifters of embodiments implement segmentation for facilitating data shifting with respect to differing bit lengths. Different data shift commands may be provided with respect to each such segment, thereby facilitating multiple data shifts in parallel with respect to various bit lengths of data.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: December 29, 2020
    Assignee: Hong Kong Applied Science and Technology Research Institute Co., Ltd.
    Inventors: Hing-Mo Lam, Man-Wai Kwan, Ching-Hong Leung, Kong-Chau Tsang
  • Patent number: 10860292
    Abstract: The invention relates to a device for generating random numbers, comprising a pair of memristors. The pair of memristors comprises a first and a second memristor, each memristor of the pair in turn comprises a top electrode, a bottom electrode and an intermediate layer adapted to switch resistance in response to predetermined voltage values applied between the top electrode and the bottom electrode. Each memristor is operatively connected to an output terminal by means of its bottom electrode. A control logic is connected to the memristors for applying suitable voltages necessary to determine a change of resistance in at least one memristor of the pair.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: December 8, 2020
    Assignee: POLITECNICO DI MILANO
    Inventors: Daniele Ielmini, Simone Balatti, Stefano Ambrogio
  • Patent number: 10853036
    Abstract: A method of generating a hardware design to calculate a modulo value for any input value in a target input range with respect to a constant value d using one or more range reduction stages. The hardware design is generated through an iterative process that selects the optimum component for mapping successively increasing input ranges to the target output range until a component is selected that maps the target input range to the target output range. Each iteration includes generating hardware design components for mapping the input range to the target output range using each of a plurality of modulo preserving range reduction methods, synthesizing the generated hardware design components, and selecting one of the generated hardware design components based on the results of the synthesis.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: December 1, 2020
    Assignee: Imagination Technologies Limited
    Inventor: Samuel Lee
  • Patent number: 10853038
    Abstract: An integrated device, for generating a random signal, includes: a first terminal; a pulse signal generator configured to generate a current pulse train on the first terminal; and a first control circuit coupled to the first terminal and configured to convert the current pulse train into a voltage signal randomly including voltage pulses greater than a threshold, the random signal containing the voltage pulses greater than the threshold.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: December 1, 2020
    Assignee: STMICROELECTRONICS SA
    Inventors: Philippe Galy, Thomas Bedecarrats
  • Patent number: 10853446
    Abstract: In one embodiment, a computer-implemented method of discrete Fourier transform (DPT), FFT, or DCT computations on a system comprising a processor is described herein. In one example, the method includes receiving, with the processor, input complex samples from memory of the system, determining input vectors based on the received input complex samples, determining a DFT radix p of p macro blocks based on the input vectors, determining p independent DFT-L vectors based on the p macro blocks with L being based on p, and generating p DFT-N output vectors without reordering or shuffling output data based on the p independent DFT-L vectors.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: December 1, 2020
    Assignee: Apple Inc.
    Inventors: Chris C. Lee, Ali Sazegari
  • Patent number: 10846056
    Abstract: A configurable SIMD multiplication circuit is provided to perform multiplication on a multiplicand operand M and multiplier operand R with varying data element sizes supported. For each result element generated based on corresponding elements of the multiplicand operand M and the multiplier operand R, the multiplication is performed according to radix-N modified Booth multiplication, where N=2P and P?3. A Booth digit selection scheme is described for improving the efficiency with which higher radix modified Booth multiplication can be implemented in a configurable SIMD multiplier.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: November 24, 2020
    Assignee: Arm Limited
    Inventors: Michael Alexander Kennedy, Neil Burgess, Zichao Xie, Karel Hubertus Gerardus Walters
  • Patent number: 10846621
    Abstract: Provided are systems, methods, and integrated circuits neural network processor that can execute a fast context switch between one neural network and another. In various implementations, a neural network processor can include a plurality of memory banks storing a first set of weight values for a first neural network. When the neural network processor receives first input data, the neural network processor can compute a first result using the first set of weight values and the first input data. While computing the first result, the neural network processor can store, in the memory banks, a second set of weight values for a second neural network. When the neural network processor receives second input data, the neural network processor can compute a second result using the second set of weight values and the second input data, where the computation occurs upon completion of computation of the first result.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: November 24, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Randy Huang, Ron Diamant, Jindrich Zejda, Drazen Borkovic
  • Patent number: 10824934
    Abstract: Described examples include an integrated circuit including a vector multiply unit including a plurality of multiply/accumulate nodes, in which the vector multiply unit is operable to provide an output from the multiply/accumulate nodes, a first data feeder operable to provide first data to the vector multiply unit in vector format, and a second data feeder operable to provide second data to the vector multiply unit in vector format.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: November 3, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mihir Narendra Mody, Shyam Jagannathan, Manu Mathew, Jason T. Jones
  • Patent number: 10824394
    Abstract: A system includes an associative memory array and a concurrent adder. The memory array includes a plurality of sections, where each section includes cells arranged in rows and columns. The memory array stores bit j from a first multi-bit number and bit j from a second multi-bit number in a same column in section j. The concurrent adder performs, in parallel, multi-bit add operations of P pairs of multi-bit operands stored in columns of a memory array. Each pair of the P pairs is stored in a different column of the array and each add operation occurs in its associated different column.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: November 3, 2020
    Assignee: GSI Technology Inc.
    Inventor: Moshe Lazer
  • Patent number: 10817288
    Abstract: A processor core comprising in its set of instructions, a combined addition and bound-checking instruction (ADDCK) defining an integer n implicitly, or explicitly as a parameter of the instruction; an adder having a width p strictly greater than n bits; and a processing circuit (MUX, 42) designed to respond to the combined instruction by activating an overflow signal (BX) when the adder generates a carry of rank n during the addition of operands of width p.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: October 27, 2020
    Assignee: UPMEM
    Inventors: Fabrice Devaux, David Furodet
  • Patent number: 10803395
    Abstract: Systems, computer-implemented methods, and computer program products to facilitate quantum domain computation of classical domain specifications are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise an input transformation component that can be adapted to receive one or more types of domain-specific input data corresponding to at least one of a plurality of domains. The input transformation component can transform the one or more types of domain-specific input data to quantum-based input data. The computer executable components can further comprise a circuit generator component that, based on the quantum-based input data, can generate a quantum circuit.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: October 13, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marco Pistoia, Jay M. Gambetta, Antonio Mezzacapo, Richard Chen, Stephen Wood, Peng Liu, Shaohan Hu, Julia Elizabeth Rice, Ivano Tavernelli, Rudy Raymond Harry Putra, Panagiotis Barkoutsos, Nikolaj Moll
  • Patent number: 10802799
    Abstract: According to an embodiment, there is provided a semiconductor device including a plurality of operation circuits each including a multiplier including a first input terminal and a second input terminal and configured to calculate a product of a value input via the first input terminal and a value input via the second input terminal, and an accumulator configured to integrate an output of the multiplier and output an integrated value that is obtained by integrating output values of the multiplier. The plurality of operation circuits are divided into groups by two manners, where by the first manner multiple operation circuits are configured to receive a common first value via the respective first input terminals, and by the second manner multiple operation circuits are configured to receive a common second value via the respective second input terminals.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: October 13, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Daisuke Miyashita
  • Patent number: 10803141
    Abstract: An associative processor includes a memory array and a controller. The memory array stores a multiplicity of N bit stochastic numbers in separate rows of a stochastic section of the memory array and each stochastic number has a same probability distribution P. The controller includes a probability calculator which receives a desired probability distribution Pdesired, determines a Boolean function of a set of the N bit stochastic numbers which produces the probability distribution Pdesired and activates associated rows of the stochastic numbers to implement the function on the rows to produce a resultant stochastic number having the probability distribution Pdesired.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: October 13, 2020
    Assignee: GSI Technology Inc.
    Inventor: Samuel Lifsches