Abstract: A system and method for deprocessing a semiconductor die is disclosed. The semiconductor dies has an active area and at least one feature in the active area. The method and system include tuning an ablation laser. The method and system further include ablating a first portion of the semiconductor die using a tuned ablation laser to mark a location of the feature. The first portion is distinct from the active area and has a center. The center of the first portion is substantially above the feature. The method and system also include deprocessing a second portion of the semiconductor die using the first portion as a guide.

Abstract: A process for the preparation of hermetically sealed electronically active microstructures involves the preparation of a plurality of microstructures and associated conductive paths and lead bond areas on a single wafer such that areas surrounding the microstructures are maintained in a planar condition. A second wafer having a plurality of microstructure-receiving cavities is placed atop the first wafer and fusion or anodically bonded. The microstructures are preferably connected to lead bond pads which lie outside the surround, the second wafer also having bond pad accessing through-holes to facilitate bonding electrical leads to the devices after sawing from the wafer. The lead-connected devices may be further encapsulated by injection molding, potting, or other conventional encapsulative packaging techniques.

Abstract: A microwave integrated circuit package is disclosed. The package consists of a package substrate, having conductive vias, at least one ground plane, and conductive transmission lines; a semiconductor die electrically and mechanically connected to the top surface of the package substrate; a continuous outer wall attached to the top surface of the package substrate and at least one interior wall at a distance from a second wall, which may be the outer wall; a lid; at least one of the transmission lines passing under the interior wall and the second wall carrying a signal of frequency F; and an impedance transformer on the transmission line between the interior wall and the second wall. In operation, the interior wall, the distance between the interior wall and the second wall and the impedance transformer cancel the discontinuity caused by the second wall whereby the reflection of the signal caused by the transmission line passing under the walls is greatly diminished.

Abstract: A method of making a semiconductor device having a thin film resistor, the method comprising the steps of: forming a first polysilicon layer on an upper surface of a field oxide layer formed on a semiconductor substrate; forming a first dielectric layer on a resultant material; ion-implanting an impurity for forming a resistor in the first polysilicon layer through the first dielectric layer; forming a second dielectric layer on an upper surface of the first dielectric layer; selectively etching the first and second dielectric layers and the first polysilicon layer to form a resistor poly (RPOLY) lower electrode; forming a second polysilicon layer on an upper surface of a resultant material; and forming a gate poly (GPOLY) by selectively etching the second polysilicon layer.

Abstract: A method of encapsulating a microelectronic assembly includes providing one or more microelectronic assemblies having one or more elements defining exterior surfaces and an array of terminals exposed at the exterior surfaces, the one or more elements defining one or more apertures through the exterior surfaces. A layer of a curable barrier material is then provided on a supporting element. The barrier layer has openings therein in a pattern corresponding to the array of terminals on the one or more microelectronic assemblies. The supporting element and the one or more microelectronic elements are then assembled together so that the layer of barrier material contacts the exterior surfaces and covers the apertures and so that the openings in the layer of barrier material are aligned with the terminals. The barrier material is then cured while in contact with the exterior surfaces to thereby form a barrier layer covering the apertures.

Abstract: A processing system includes a plurality of types of internal processing machines that perform various processes on a semiconductor substrate and an interface section that delivers and receives the semiconductor substrate to and from an external exposure machine for performing an exposure process on the substrate subjected to a resist coating process, wherein the interface section includes a transfer unit for taking in the substrate subjected to a specific process from at least one of the internal processing machines and transferring the substrate and a substrate table unit for temporarily holding the substrate to transfer the substrate between the internal processing machine and the external exposure machine via the transfer unit.

Abstract: Aspects for device and package separation of a multi-layer integrated circuit device attached at a frontside to an integrated circuit package are described. In an exemplary method aspect, the method includes slicing through material coupling the multi-layer integrated circuit to the integrated circuit package with a high power water stream. The slicing further includes cutting through solder bump material. Additionally, the multi-layer integrated circuit device is utilized for device analysis from a frontside following separation from the integrated circuit package by the step of slicing.

Abstract: A method of making a stacked microelectronic assembly such as a semiconductor chip assembly and its resulting structure includes providing a flexible substrate having a plurality of attachment sites and conductive terminals and including a wiring layer with leads extending to the attachment sites. The method includes assembling a plurality of microelectronic elements to the attachment sites and electrically interconnecting the microelectronic elements and the leads so that the electrically connected microelectronic elements are movable relative to the flexible substrate. The flexible substrate is then folded so as to stack at least some of the microelectronic elements in substantially vertical alignment with one another to provide a stacked assembly with the conductive terminals exposed at the bottom end of the stack. The stacked assembly is held in place using a thermally conductive adhesive and/or a mechanical element.

Abstract: A semiconductor package provided with a reinforcing plate on the side of the lead joined face of which a chip housing concave portion is formed, a semiconductor chip housed and fixed in the chip housing concave portion of this reinforcing plate, a plurality of leads joined and held on the lead joined face of the reinforcing plate, the inner lead section of which is joined to the semiconductor chip via a bump and in the outer lead section of which a protruded electrode is formed, a solder resist film formed on the lead except the bump formed area and the electrode formed area of this lead and a polyimide film formed on the side of the inner lead section of the lead on the solder resist film and the manufacturing method are disclosed and hereby, the quality of the semiconductor package with ultra-multipin structure is stabilized.

Abstract: A plastic encapsulated integrated circuit package is disclosed which comprises a multilayer ground plane assembly bonded to a lead frame with an integrated circuit die bonded to the composite assembly. The multilayer ground plane assembly is first formed by bonding together a metal sheet, such as a copper sheet, and a thermally conductive insulating layer, such as a thermally conductive polyimide material, to which is also bonded a layer of a b-stage adhesive material. The ground plane assembly may be bonded to the lead frame by placing the b-stage adhesive layer of the ground plane assembly against the lead frame and heating the ground plane assembly and lead frame to a temperature of from about 120.degree. C. to just under 200.degree. C. for a time period not exceeding about 10 seconds to bond the b-stage adhesive layer to the lead frame without oxidizing the lead frame.

Abstract: A design for a picker nest which protects any fragile component, such as a bare IC die, mounted on an IC package when the picker nest is holding the IC package for testing. The picker nest of the present invention includes a picker nest head having a picker nest opening with a vacuum suction. The fragile component fits within the picker nest opening as the picker nest is holding the IC package such that no contact force is exerted on the fragile component. The picker nest of the present invention also includes a conductive seal surrounding the perimeter of the picker nest opening for sealing in the vacuum suction within the picker nest opening. The conductive seal is a silicon-based sponge for effectively sealing in the vacuum suction at various temperatures. At least one supporting bar disposed on the picker nest head exerts a force against the IC package substrate toward test contacts of the testing system during testing of the IC package to ensure proper contact of the IC package pins to the test contacts.

Abstract: A sensor having high sensitivity is formed using a suspended structure with a high-density tungsten core. To manufacture it, a sacrificial layer of silicon oxide, a polycrystal silicon layer, a tungsten layer and a silicon carbide layer are deposited in succession over a single crystal silicon body. The suspended structure is defined by selectively removing the silicon carbide, tungsten and polycrystal silicon layers. Then spacers of silicon carbide are formed which cover the uncovered ends of the tungsten layer, and the sacrificial layer is then removed.

Abstract: Electrically conductive lamina are attached by an electrically insulating, thermally conductive adhesive and/or solder to one or more semiconductor devices such as chips and extend beyond the periphery of the chip or chips to form heat sink fins. Electrical connections may be made between such chips through holes (e.g. by a wire or plated through hole) in the electrically conductive lamina lined with an insulating material such as the electrically insulating adhesive to provide a structurally robust assembly. Surface pads and connections may overlie patterns of insulator on the lamina. A further lamina can be wrapped around lateral sides of the assembly to provide further heat sink area and mechanical protection for other heat sink fins. A graphite/carbon fiber composite matrix material is preferred for the lamina and the coefficient of thermal expansion of such materials may be matched to that of the semiconductor material attached thereto.

Abstract: A method for forming a semiconductor device in a semiconductor device manufacturing apparatus (20) having a sensor (30) activated extensible shuttle (28). In a fabrication environment shuttle (28) is housed within semiconductor device manufacturing apparatus (20), where an outer door (32) is closed flush with an outer wall of the apparatus (20). As a substrate carrier (38) is moved near the apparatus (20), sensor (30) activates opening of outer door (32) and extension of shuttle (28) out of the apparatus (20) into the fabrication environment. In one embodiment, shuttle (28) has a sensor which is used to determine if carrier (38) is placed on shuttle (28) within a predetermined time, allowing retraction of shuttle (28) until it is required. The present invention increases the available operative space within the fabrication environment, and provides a clean mini-environment within apparatus (20).

Abstract: Semiconductor packaged and methods for packaging semiconductor devices are provided. A method in accordance with the invention may include the steps of: attaching solder bumps on bonding pads of a wafer; cutting the wafer into individual chips, and attaching the chips to an interface board; coupling the interface board with a lead frame; and wire-bonding the bump pads of the interface board and the inner leads of the lead frame, and carrying out a molding process.

Abstract: A vacuum processing system including two or more processing units for processing wafers and a transferring unit for carrying the wafers. In this system, even when any one of the processing units becomes inoperable because of a failure, the operation of the system can be continued, and even when a processing unit in the system requires repair or maintenance at the time of the start of operation, the system can be operated using other operable processing units without subjecting the operator to danger due to improper operation. As a result, the working efficiency of the system can be increased and the safety of the operator can be secured. In this system, the cleaning of the interior of each processing unit is performed by carrying a cleaning dummy wafer into each processing unit using the transferring unit, followed by recovery of the dummy wafer after cleaning, so that processing of wafers in the processing unit can be carried out once again.

Abstract: A semiconductor device having gate electrodes with different gate insulators and a process for fabricating such device is provided. Consistent with one embodiment of the invention, a semiconductor device is provided in which a first gate insulator is formed over a first region of a substrate. A second gate insulator, different than the first gate insulator, is formed over a second region of the substrate. Finally, one or more gate electrodes are formed over each of the first and second gate insulators. The first gate insulator may, for example, have a permittivity and/or a thickness which is different from that of the second gate insulator. For example, the first gate insulator may have a permittivity greater than 20, and the second gate insulator may have a permittivity less than 10.

Abstract: A method and apparatus for a reinforced leadframe to substrate attachment in a semiconductor assembly. In one embodiment, a printed circuit board having a plurality of electrically coupled electrical contact regions and wire bond areas formed thereon has a leadframe attached thereto such that each of the bonding fingers of the leadframe is coupled to a respective electrical contact region on the printed circuit board. A ribbon of B-staged epoxy is disposed on the leadframe such that said leadframe is disposed between the ribbon of B-staged epoxy and the printed circuit board. An integrated-circuit die is mounted on the printed circuit board with the bonding fingers of the leadframe peripherally surrounding the integrated circuit die. The bonding pads on the integrated-circuit die are electrically coupled to respective wire bond areas on the printed circuit board.

Abstract: A plurality of substrates is closely stacked together in a Rapid Thermal Processing (RTP) chamber, and the stack is processed simultaneously.

Abstract: A method for manufacturing a buried-channel pMOSFET device that utilizes a plasma doping technique to form a very shallow P-type channel layer on the top surface of a sub-micron buried-channel pMOSFET. The buried-channel pMOSFET device formed by the method has a higher current drivability and a higher anti-punchthrough resistance.