Patents Examined by Michael E Moats, Jr.
  • Patent number: 9865480
    Abstract: The present invention relates to an under-fill dam with high detection probability that is composed of a dry film solder resist and provided in the form of a fence around a chip device in order to prevent leaks of an under-fill material filled in a gap between a substrate and the chip device.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: January 9, 2018
    Assignee: LG CHEM, LTD.
    Inventors: Byung-Ju Choi, Woo-Jae Jeong, Bo-Yun Choi, Kwang-Joo Lee, Min-Su Jeong
  • Patent number: 9839132
    Abstract: In a component-embedded substrate, a component and wiring block units are embedded in a component-embedded layer; conductive layers are located on all surfaces of the wiring block units; the component and the wiring block units are arranged such that lower surface side conductive layers of the wiring block units and electrodes of the component contact lower surface side wiring layers; via-hole conductors are located in respective upper positions relative to upper surface side conductive layers of the wiring block units and the electrodes of the component; and upper surface side wiring layers of the component-embedded layer are thus electrically connected to upper surface side conductive layers of the wiring block units, and the electrodes of the component by the via-hole conductors.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: December 5, 2017
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Masanori Fujidai, Isamu Fujimoto
  • Patent number: 9780460
    Abstract: There is provided an electric cable connection terminal. A first connection part is configured to connect the one electric cable thereto. A second connection part is configured to connect the other electric cable thereto. A waterproof member is configured to be melted to seal leading end portions of core wires of the electrics cable when being heated and configured to be solidified to waterproof the leading end portions when being cooled. An accommodation part accommodating the waterproof member therein is provided between the first and second connection parts. A thermal shrinkage member is provided to cover the first and second connection parts and the accommodation part and configured to be shrunken when being heated to closely contact the first and second connection parts and the accommodation part. When the cables are connected to the first and second connection part, respectively, the core wires are arranged at an interval.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: October 3, 2017
    Assignee: YAZAKI CORPORATION
    Inventor: Naoki Koto
  • Patent number: 9735477
    Abstract: Terminal pin for electrically connecting a carrier of electrical leads or an electronic component by means of a solder connection between the carrier or component and the terminal pin, wherein an end of a pin body is provided with a swaged cap of a material which is harder than the material of the pin body and which has an outer surface which is suitable for making the solder connection, wherein the cap has an inner circumferential edge where the cap is at least locally narrowed to inside of the outer circumference of the pin body, and wherein there is no additional material between the pin body and the cap.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: August 15, 2017
    Assignee: BIOTRONIK SE & Co. KG
    Inventors: John Roos, Frederik Sporon-Fiedler
  • Patent number: 9685776
    Abstract: A sealing unit (28) fits within the sealing unit opening (26) of a housing 22. The sealing unit (28) including a sealant arrangement (32) that define a plurality of cable ports (30). The sealing arrangement is also configured for providing a peripheral seal between the housing (22) and the sealing unit (28). The sealing unit (28) includes an actuation arrangement (31) for pressurizing the sealant arrangement (32) within the sealing unit opening (26). The sealant arrangement (32) includes a plurality of sealing modules (33a-33e) each sized to form only a portion of the pressure actuated sealant arrangement (32).
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: June 20, 2017
    Assignee: CommScope Connectivity Belgium BVBA
    Inventors: Philippe Coenegracht, Mohamed Aznag, Paul Joseph Claes, Dirk Jozef G. Van De Weyer, Maarten Michiels, Diederik Houben, Pieter Doultremont, Eddy Maes, Geert Van Genechten, Maddy Nadine Frederickx, Emilie De Groe
  • Patent number: 9681547
    Abstract: An electronic device includes: a housing including an opening; a connector configured to be exposed from the opening and to allow a connection member to be coupled thereto; and a cable configured to cover at least a portion of a gap between the connector and the opening and to be electrically coupled to the connector.
    Type: Grant
    Filed: March 20, 2013
    Date of Patent: June 13, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Daisuke Mihara, Hirohisa Nakabayashi, Ikki Tatsukami
  • Patent number: 9681566
    Abstract: An electronic arrangement (1) comprising a carrier (2), on which at least one connecting area (6) is arranged. At least one electronic component (3a, 3b, 3c) is fixed on the connecting area (6) by means of a contact material (4). A covering area (5) surrounds the connecting area (6) on the carrier (2). At least one covered region (15, 16, 17, 18, 19) is covered by a covering material (10). The covering material (10) is designed in such a way that an optical contrast between the covering area (5) and the covered region (15, 16, 17, 18, 19) is minimized.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: June 13, 2017
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Thomas Bemmerl, Simon Jerebic, Markus Pindl
  • Patent number: 9674970
    Abstract: In a method of manufacturing a module board, an electronic component is mounted on a first principal surface of a small board. A cavity defining a through hole is formed in a core board. The electronic component is housed in the cavity by mounting the small board on a surface electrode arranged around the cavity. Resin layers are formed on both principal surfaces of the core board, and resin flows through a gap between the core board and the small board. Hence, the inside of the cavity is filled with the resin, and the electronic component is sealed with the resin.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: June 6, 2017
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Issei Yamamoto, Akihiko Kamada
  • Patent number: 9673598
    Abstract: A cover assembly for an electrical box, such as a fire-rated poke through, includes a frame defining an opening, the frame including a first frame location and a second frame location, the first frame location being substantially opposite the second frame location, a cover movable between a closed position over the opening and an open position away from the opening, the cover having a perimeter including a proximal end and a distal end, the proximal end being substantially opposite the distal end, and a hinge attaching the cover to the rear frame portion, the hinge having two substantially parallel pivot axes, at least one of which is movable towards and away from the other, one pivot axis located at the first frame location and the other pivot axis located at the proximal end of the cover.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: June 6, 2017
    Assignee: Hubbell Incorporated
    Inventors: Joseph V. DeBartolo, Jr., Sorin I. Mortun, Stephen R. Ewer
  • Patent number: 9668346
    Abstract: A terminal portion configured to obtain electrical connection with a printed circuit board includes a first signal pad that is formed in a first conductor layer and is electrically separated from a ground layer, a pair of first ground pads that is formed in the first conductor layer to sandwich the first signal pad and is connected to the ground layer, a second signal pad that is formed in a second conductor layer and is connected to a signal line, a pair of second ground pads that is formed in the second conductor layer to sandwich the second signal pad and is electrically separated from the signal line, a third signal pad formed in a third conductor layer, and a pair of third ground pads formed in the third conductor layer to sandwich the third signal pad. The second signal pad is wider than the third signal pad.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: May 30, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Mizuki Shirao, Nobuo Ohata, Nobuyuki Yasui, Hiroshi Aruga
  • Patent number: 9653656
    Abstract: An LED package with trenches traversing a die pad to provide a mechanical interlock mechanism to strengthen bonding between the die pad and an insulator such that de-lamination is less likely to occur between the die pad and the insulator. A chip carrying region is defined by a barrier portion formed by the insulator in the trenches and in gaps between electrodes and the die pad, such that a light converting layer is confined within the barrier portion.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: May 16, 2017
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Hsun-Wei Chan
  • Patent number: 9648761
    Abstract: A cover covers a fuse unit to which a terminal is fixed in a manner such that a nut is fastened onto a bolt placed with the tip thereof facing outward. The cover is provided, on the inner surface thereof in a position corresponding to the nut, with a protrusion having a height set in a manner such that the protrusion does not interfere with the nut located in a fastened position, but interferes with the nut located in another position other than the fastened position. A thin portion is formed on the circumference of the protrusion.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: May 9, 2017
    Assignee: YAZAKI CORPORATION
    Inventor: Yusuke Matsumoto
  • Patent number: 9648794
    Abstract: The present disclosure provides a wiring board including a thin film member configured to include an inorganic dielectric film formed over an overall area of a mounting face thereof for an electronic part, a first conductive film formed over an overall area of one of faces of the inorganic dielectric film and including a plurality of patch electrode portions disposed in a predetermined pattern corresponding to a predetermined electromagnetic band gap structure in at least part of the area, and a second conductive film formed over an overall area of the other face of the inorganic dielectric film.
    Type: Grant
    Filed: April 2, 2013
    Date of Patent: May 9, 2017
    Assignee: SONY CORPORATION
    Inventor: Shinji Rokuhara
  • Patent number: 9613732
    Abstract: A wire harness manufacturing method prevents inadvertent deformation of thermoplastic material and separation of thermoplastic material. A predetermined part of an electric wire 91 is accommodated in a through hole of a tubular body formed by connection between a first and second nest members (123, 124) of a nozzle (12), by integrally connecting first and second case body members (121, 122) of the nozzle (12), with the predetermined part of the electric wire 91 therebetween. An approximately tubular covering member (92) covering the predetermined part of the electric wire (91) is molded integrally with the thermoplastic material, by discharging thermoplastic material plasticized by a material plasticizing unit (11) from thermoplastic material discharge orifices (1213) and (1223) in the nozzle (12) to the outer periphery of the electric wire (91), while moving the electric wire (91) and the nozzle (12) relatively to each other.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: April 4, 2017
    Assignees: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Osamu Sato
  • Patent number: 9612705
    Abstract: An electroconductive film includes a transparent conductive layer having a plurality of electrodes which extend in one direction. The electrodes have different electrode widths depending on the site, and are configured of a plurality of polygonal cells formed of fine metal wires. The sizes of the respective cells are not uniform. The average size of the cells is greater than or equal 1/30, and less than 1/3, of the narrowest width of the electrodes. The average size of the cells is uniform in the electrodes overall.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: April 4, 2017
    Assignee: FUJIFILM Corporation
    Inventor: Hiroshige Nakamura
  • Patent number: 9606587
    Abstract: A device including a heat-absorbing component, and one or more heat-generating components. At least one heat-generating component is located in proximity to an inner surface of the heat-absorbing component, and a gap exists between the at least one heat-generating component and the inner surface of the heat-absorbing component. The device further including an insulator, located in the gap, including an insulator structure enclosing atmospheric pressure gas, where the atmospheric pressure gas has a thermal conductivity lower than air.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: March 28, 2017
    Assignee: Google Inc.
    Inventor: William Hamburgen
  • Patent number: 9589694
    Abstract: An alloyed 2N copper wire for bonding in microelectronics contains 2N copper and one or more corrosion resistance alloying materials selected from Ag, Ni, Pd, Au, Pt, and Cr. A total concentration of the corrosion resistance alloying materials is between about 0.009 wt % and about 0.99 wt %.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: March 7, 2017
    Assignee: Heraeus Deutschland GmbH & Co. KG
    Inventors: Murali Sarangapani, Ping Ha Yeung, Eugen Milke
  • Patent number: 9591744
    Abstract: A display device includes an upper substrate on a lower substrate, a driver integrated chip (IC) on the lower substrate, the driver IC and upper substrate contacting different parts of the lower substrate, a plurality of bumper units along edges of the driver IC, and a deformation preventing bumper unit between the bumper units, the deformation preventing bumper unit being configured to prevent the driver IC from being deformed.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: March 7, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Joon-Sam Kim, Jong-Hwan Kim, Sang Won Yeo, Sang-Urn Lim, Suk-Ho Choi
  • Patent number: 9585247
    Abstract: An anisotropic conductive film includes a first connection layer and a second connection layer formed on one side of the first connection layer. The first connection layer is obtained by photo-radical polymerization of a photo-radical polymerizable resin layer containing an acrylate compound and a photo-radical polymerization initiator. The second connection layer includes a thermal- or photo-, cationic or anionic polymerizable resin layer containing an epoxy compound and a thermal- or photo-, cationic or anionic polymerization initiator, or a thermal- or photo-radical polymerizable resin layer containing an acrylate compound and a thermal- or photo-radical polymerization initiator. Conductive particles for anisotropic conductive connection are arranged in a single layer on a second connection layer-side surface of the first connection layer.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: February 28, 2017
    Assignee: DEXERIALS CORPORATION
    Inventor: Yasushi Akutsu
  • Patent number: 9560771
    Abstract: An apparatus includes a substrate having a surface and a plurality of solder balls arranged on the surface to form a ball grid array. A portion of the plurality of solder balls is arranged to have a pitch between adjacent solder balls. The adjacent solder balls having the pitch have a shape of a truncated sphere. At least one solder ball of the plurality of solder balls is included in a solder island on the surface having a shape that is different than the shape of the truncated sphere.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: January 31, 2017
    Assignee: OmniVision Technologies, Inc.
    Inventors: Ying-Tang Su, Wei-Feng Lin, Kah-Ong Tan