Abstract: In a semiconductor random access memory device of the type having two or more data lines arranged in association with a single data input or output terminal is provided a memory testing circuit which is characterized in that test data is supplied to every one of the data lines and is written all at a time into a plurality of memory cells which may include those located adjacent each other, wherein the number of the memory cells into which test data is to be written simultaneously depends on the data lines to be selected so that different pieces of data can be respectively written into the individual memory cells.