Abstract: According to the current invention, there is provided a system for transferring data into and out of a first-in, first-out (FIFO) data buffer. The buffer has a read pointer and a write pointer. The system comprises a comparator circuit, multiple counter blocks, and multiple flag registers. The counter blocks and flag registers are connected to a system clock to provide timing information and capacity indications to the comparator. The comparator circuit continuously monitors the multiple counter blocks, thereby tracking buffer pointer positions. The flag registers indicate relative buffer capacity and provide early indication to the system that the buffer is almost full or almost empty in appropriate conditions. The comparator circuit continuously evaluates the read and write counter blocks and the flag registers to determine the ability of the buffer to accept or transmit data.

Abstract: An interactive computer system responsive to a user's voluntary and autonomic nervous system responses. The interactive computer system includes a computer, a voluntary input device requiring intentional actuation by the use, a sensor to detect autonomic nervous system responses, an interface device, and an output device. The voluntary input devices and output devices communicate with the computer. The sensors detect autonomic nervous system signals of a user and generate signals representative of the responses. The interface device communicates with the sensors and the computer. The interface device conditions the signals generated by the sensors and transmits the signals to the computer. The computer is responsive to the signals and produces an output command which is in part dependent upon the signals. The output device responds appropriately to the output command produced by the computer.

Abstract: A master (1) and a slave (3) are connected via a transmission line (5) for sending a clock CL; another transmission line (6) for bidirectionally sending data DT; and still another transmission line (7) for sending a control signal CE. Having turned a control signal CE into "L," the master (1) transmits an address code as data DT to the slave (3). Referring to the content of the transmitted address code, the slave (3) detects whether it is a data transmission from the master (1) to the slave (3) or vice versa. While a control signal CE remains "H," data transmission takes place. Data output from the slave (3) to the data line (6) is managed by a bus driver (22). The bus driver (22) is turned off during a period from when the clock CL became "H" to when a control signal CE becomes "L" after data transmission so that data transmission from the master (1) will not be adversely affected.

Abstract: Disclosed are methods and apparatuses for use with a host computer system that optimize the timing and sizing of data blocks that are part of an ATM PDU that is to be transmitted over an ATM network. The data blocks are transferred from the host's memory to a local memory in a network interface circuit. The network interface circuit includes a memory access circuit, a segmenting circuit, a local memory, and a scheduling circuit. The memory access circuit accesses the host's memory and fetches an initial size block of a data packet therefrom and supplies the block of the data to the segmenting circuit which segments the block of the data into a plurality of linked cells. The plurality of linked cells are then stored in the local memory. The scheduling circuit retrieves the linked cells in a predetermined order and transmits each of them over a network connection at a specific time.

Abstract: A method for controlling whether or not to display the status monitor of a device. When a certain application program outputs a printing command and the status monitor of the printer is set to be displayed, data indicative of the application program is first obtained and compared with a list of problem application programs. If the name is not in the list, then the printing status monitor is displayed. However, if the name is found in the list, the status monitor is not displayed. This method increases efficiency of work for the user and prevents such problems as the computer hanging up or the programs being forcibly closed.

Abstract: A memory controller having request queue and snoop tables is provided for functioning with bus interface units interposed between a multiple processor bus and individually coupled to the respective processors in a complex incorporating a multitude of processors, where each bus interface unit includes block snoop control registers responsive to signals from a system memory controller including enhanced function supportive of I/O devices with and without block snooping compatibility. The tables are compared to minimize and more efficiently institute snoop operations as a function of the presence or absence of the same listings in the tables. The BIU provides functionality for the bus of the multiple processors to be processor independent. This architecture reduces the number of snoop cycles which must access the processor bus, thereby effectively increasing the available processor bus bandwidth. This in turn effectively increases overall system performance.

Abstract: A bus bridge mutually connects a CPU bus to which a CPU and a corresponding cache memory having a write-back scheme are coupled, an I/O bus to which a bus master is coupled, and a main memory which is commonly accessed through the CPU bus or I/O bus. In response to an access request from the bus master to the main memory, a cache snooping section snoops a cache memory to see whether an address in the access request satisfies a cache hit or miss, and data corresponding to the address is dirty or clear. In response to a snooping result by the cache snooping section indicating that the cache hit has occurred and the data is dirty, a write-back control section writes back the data from the cache memory in the main memory. In the case where the access request indicates a read request, a data bypass section directly transfers the data from the cache memory onto the I/O bus while the write-back control section performs writing back.

Abstract: A method and device for displaying the internal information of a computer, such as CPU type, CPU operating speed, memory size, real time clock, BIOS version, and OS version, and those data which are inputted by user, is disclosed. The displaying device is provided with a displaying unit mounted on the front panel of the computer to display the information signals which are transmitted from the computer through the speaker output port on the mother board of the computer. The device further includes a spare power supply to provide power energy for displaying the information when the computer is shut down.

Abstract: A method of controlling an input/output (I/O) device connected to a computer to facilitate fast I/O data transfers. An address space for the I/O device is created in the virtual memory of the computer, wherein the address space comprises virtual registers that are used to directly control the I/O device. In essence, control registers and/or memory of the I/O devices are mapped into the virtual address space, and the virtual address space is backed by control registers and/or memory on the I/O device. Thereafter, the I/O device detects writes to the address space. As a result, a pre-defined sequence of actions can be triggered in the I/O device by programming specified values into the data written into the mapped virtual address space.

Abstract: A method and system for associating and selecting a set of I/O components as a source or destination of I/O data directed to or from an application. A set of I/O components are modeled as a component object model which becomes a generic access device (GAD) for those components. Relevant interfaces to the components are instantiated within the GAD. The GAD then hands out the interfaces to applications wishing to access the I/O devices modeled by the GAD. The application is thereby enabled to carry out meaningful communication with the I/O devices to which the GAD provided interfaces.

Abstract: An information handling system includes one or more processing units, a memory management unit, connected to the processor, and to a memory system, a cache management unit, one or more levels of cache memory associated with the one or more processors, an I/O controller connected to a bus which connects to the processing units and to the memory systems and to cache, the I/O controller controlling various input/output devices such as a keyboard, a mouse, a display device, communications adapters and the like, and a remote storage controller for controlling one or more direct access storage devices. Cache management unit further includes an optimized block transfer circuit for identifying starting and ending addresses of modified segments of data blocks and the cache unit.

Abstract: A computer system implements a standard modem without the use of a microcontroller. Instead, a digital signal processor is provided on an expansion card, but with direct links to the computer system itself. The code usually implemented in the microcontroller is instead implemented as a virtual modem controller to be called by the operating system of the computer itself. Further, this virtual modem controller includes a virtualized UART, that appears to the operating system software as a hardware UART, with entry points for calls to replace input/output instructions. In this way, standard device driver code written to execute input/output operations is easily converted to operate with the "virtualized" UART.

Abstract: The invention provides a character and picture data compression apparatus which can collectively compress document data of the character code form and still picture data and moving picture data of the bit map form. A conversion section converts document data of the character code form into those of the bit map form. A display image composition section composes the document data of the bit map form, still picture data of the bit map form and a first one frame of moving picture data into a display image of the first page, and then produces, for each of the succeeding frames, a display image wherein the moving picture data portion in the display image of the first page is replaced with moving picture data of the frame. A difference processing section calculates, for each of the display images of the succeeding pages, a difference from the display image of the immediately preceding page in the bit map form.