Abstract: Aspects of the present invention provide a solution for responding to a change in an environment of a computer system. In an embodiment, a set of triggered controlled event listener learners (T-CELLs) are deployed in the computer system. Each T-CELL of the set of T-CELLs is a self-contained, persistent software construct. Further, each T-CELL has the ability to communicate with the other T-CELLs in the computer system. These T-CELLs can, in response to detecting a change in the computer system, automatically create a new T-CELL to respond to the change.

Abstract: Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.

Abstract: During a power-on sequence of a computer system, it is detected whether the computer system is connected over a first type of connection to a terminal. In response to detecting that the computer system is connected over the first type of connection to the terminal, settings of the computer system are configured to be compatible with a first type of operating system.

Abstract: Described is a method and system for initiating configuration of a modem connected to a mobile device. The system and method provide a mechanism for guiding a user through the setup process in order to simplify the user's connectivity to a network using the modem. In one embodiment, the mechanism monitors for when a modem is connected to the mobile device. When a modem is connected for the first time, the mobile device launches a wizard utility that directs the user's configuration of the connected modem. The user is able to choose from performing an initial configuration of the modem, or migrating settings of a previously connected modem to establish the connected modem's settings. Thus, the user is guided through the configuration process, increasing the discoverability of the modem and simplifying its setup for the user.

Abstract: A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link interfaces to any of the memory controllers, a write buffer and read cache for each memory device and a read synchronization module. The read synchronization module includes a write pointer, a read pointer and a buffer. The write pointer is incremented in response to the receipt of read data. The read pointer increments in response to coupling of the read data from the memory hub. A comparator compares the read pointer an the write pointer, and the comparison is used to adjust the memory timing.

Abstract: Maintaining synchronization when sending/receiving multiple channels of data with a corresponding common reference clock signal. Synchronization signals (e.g., pulses) are generated periodically and the timing of channels is adjusted. In an embodiment, multiple sequences of parallel data elements are received on corresponding parallel data channels using a first common clock signal. Each sequence of parallel data elements is converted to a corresponding sequence of serial data elements. The serial data elements are transmitted on a corresponding serial channel using a serial clock as a common reference. A synchronization signal may be generated periodically with a time period of (the number of bits in each parallel data element×the time period of the serial clock), wherein ‘×’ represents multiplication operation. As the parallel data channels are synchronized in short intervals, synchronization is maintained.

Abstract: In a parallel processing system by an OS for single processors which operates an OS and an existing application for single processors on a multiprocessor to realize parallel processing by the multiprocessor with respect to the application, a processor on a first processor side receives a request for activating or stopping a processor from a unit of work on any of the processors and controls a power supply management device of the OS for single processors to conduct activation or stop of the requested processor, while the processor requested to be activated or stop executes processing necessary for the activation or stop based on a notification from the first processor side.

Abstract: An apparatus, system, and method are disclosed for fastload code update on a communications adapter. The apparatus includes an image load module, a memory initialization module, and an image overlay module. The image load module is configured to load a copy of a new code image in a memory on the communications adapter. The memory also concurrently stores a copy of an old code image used by the communications adapter. The memory initialization module is configured to invoke the new code image to perform a memory initialization operation. The memory initialization module may perform the memory initialization operation concurrently with ongoing I/O requests possibly accepted, but not necessarily processed, by the old code image. The image overlay module is configured to overlay the old code image with the new code image. The fastload code update minimizes the time that the communications adapter is off-line to overlay the old code image with the new code image and reinitialize the communications adapter.

Abstract: In a backup system 310, 340, 350, or 360, a controller 300 controls operation of a multi-source audio apparatus MMSA. An operation status holder 310 holds operation status information Dbk of the multi-source audio apparatus MMSA. A non-volatile memory 340 stores the operation status information Dbk. A capacitor 360 as a power storage means stores part Pt of operating power. An operating power detector 350 (Sps) detects whether or not the operating power is being supplied. An operation status information write device 310 selectively writes the operation status information Dbk into the non-volatile memory 34 depending on whether or not the operating power is being supplied.

Abstract: Power sourcing equipment providing a plurality of power sources for connection over communication cabling to a single powered device, the power sourcing equipment comprising: a first power source; a second power source; a control circuit; a current sensor adapted to monitor an output current of the first power source, the current sensor being operatively connected to the control circuit; and a voltage regulating means associated with one of the first power source and the second power source, the voltage regulating means being responsive to the control circuit, the control circuit being operative responsive to the monitored output current to operate the voltage regulating means so as to maintain the monitored output current within a pre-determined range.

Abstract: A method to reduce and thereby improve the initial program load time of a computing apparatus operating system and thus provides for near instantaneous user interaction. When practicing the instant invention, a computing apparatus operating system or application processing component is loaded neither sequentially nor completely, but rather on an as required basis. The invention's “required only” loading of processing components persist through subsequent operation and shut down of the computing apparatus with each loaded task creating a checkpoint record of processing modifications to non-volatile memory. Such checkpointing allows shut down processing of the apparatus to consist of merely flushing memory buffers in the apparatus checkpointed non-volatile memory of the apparatus to permanent storage and powering off of the apparatus, with subsequent initial program load (IPL) sequencing referencing the checkpointed records to minimize future system initialization elapsed time.

Abstract: A method of designing a system on a chip (SoC) to operate with varying latencies and frequencies. A layout of the chip is designed with specific placement of devices, including a bus controller, initiator, and target devices. The time for a signal to propagate from a source device to a destination device is determined relative to a default propagation time. A pipeline stage is then inserted into a bus path between said source device and destination device for each additional time the signal takes to propagate. Each device (i.e., initiators, targets, and bus controller) is designed with logic to control a protocol that functions with a variety of response latencies. With the additional logic, the devices do not need to be changed when pipeline stages are inserted in the various paths. Registers are utilized as the pipeline stages that are inserted within the paths.

Abstract: A synchronous input to output protocol translator supporting multiple reference oscillator frequencies and fixed latency data computation and chip crossing circuits enables implementation of a method for delaying osc2 relative to osc1 in a configurable way to provide a constant, minimal Tptcc over a range of refosc frequencies between circuits for data transferred. It requires that the data transferred from a register R1 be sent over multiple wires via configurable delay circuitry for osc2, capture circuitry at the input to R2, and a circuit to transfer a synchronizing signal from a non-delayed clock domain to a delayed clock domain. Relative to osc1, osc2 is a delayed, synchronous clock.

Abstract: A method and system for reducing power consumption in a programmable logic device (PLD) is provided. The power consumption may be reduced by preferably continually considering power consumption as a factor in circuit design during the synthesis, placement, routing, and period following routing of the programmable logic device.

Abstract: An apparatus, a method and a storage medium for carrying out a deskew among multiple lanes for use in a division transmission of large-capacity data.

Abstract: A system and method to determine a presence of devices coupled to one a more peripheral buses in a system, and dynamically reducing power consumption of a subset of the devices that are present, based on correlating application/device association and a predetermined power source budget. In one embodiment, the reducing of the power consumption is performed dynamically by having an agent reduce the power limit in a device register(s) corresponding to the subset of devices. Furthermore, in one embodiment, the power resource budget is based at least in part on a user-selected power/performance level.

Abstract: A method for overload detection according to one embodiment of the invention includes a control process and a data process. In response to a timing signal, the control process sets a state of a timing indicator. Upon execution of a time-constrained operation, the data process checks the state of the timing indicator. In other embodiments, subsequent to an overload detection, an auxiliary data process is configured to execute in a mode that consumes fewer processing cycles.

Abstract: A memory module and an apparatus having a memory module for generating an internal clock synchronized to an external clock, the memory module being operated based on the internal clock as an operation clock and includes a first DLL circuit for generating a first internal clock from an external clock in a first frequency band, a second DLL circuit for generating a second internal clock from an external clock in a second frequency band different from the first frequency band, and a selector for selecting any of the first internal clock generated by the first DLL circuit and the second internal clock generated by the second DLL circuit, and outputting the selected clock as the operation clock of the memory module.

Abstract: A method and system for controlling a startup sequence in a computer system is disclosed. The method and system include monitoring at least one aspect of a plurality of startup applications launched during the startup sequence. The method and system further include analyzing the at least one aspect of the plurality of startup applications based on at least one criteria. The at least one criteria indicates whether a portion of the plurality of startup applications is extraneous at startup. The method and system further include automatically removing at least one of the portion of the plurality of startup applications from the startup sequence.

Abstract: A network power system that is capable of communicating and resolving various inline power allocation issues. The system includes a power source equipment having at least one output power interface capable of transmitting inline power, at least one powered device having an input power interface capable of receiving inline power, and a first transmission media that is coupled between the power source equipment and the at least one powered device. Either or both of the power source equipment and the at least one powered device includes a negotiator that is capable of communicating and resolving the at least one inline power allocation issue. The negotiator, independently or in combination with other negotiators, reaches a negotiated decision and performs at least one response function in an effort to resolve the at least one inline power allocation issue. The system may have a multi-point layout or be experiencing a power outage condition.