Abstract: After a polysilicon semiconductor film 5 and a first gate oxide film 6 are formed on a transparent insulating substrate 1, the semiconductor film 5 and the first gate oxide film 6 are patterned into an island shape to form an island part. At this time, an overhang part 8 of a visor shape is formed where side end surfaces of the first gate oxide film 6 and the semiconductor film 5 are not aligned and an end part of the first gate oxide film 6 projects slightly from a position of a side end surface of the semiconductor film 5. The overhang part 8 is removed, for example, during cleaning, which thus enhances yield.

Abstract: Disclosed herein is a process for assembling an integrated circuit, as well as the assembly resulting from the process, employing a surface treatment of bondpad surfaces. In one aspect, a method of assembling an integrated circuit includes providing a substrate having electrical terminals on a first side of the substrate and a bondpad on a second side of the substrate opposing the first side. In this embodiment, the bondpad is electrically coupled to at least one of the terminals on the first side. In addition, the method includes mounting an integrated circuit chip to the first side of the substrate, where the integrated circuit component has a lead adapted to be wire-bonded to the terminal. The method further includes removing oxidation from the bondpad, where the bondpad is adapted to be metallurgically bonded to a trace on a printed circuit board. Moreover, this embodiment of the method includes metallurgically bonding the bondpad to the trace.

Abstract: The subject invention pertains to a method of spark processing silicon and resulting materials. The subject invention also relates to electroluminescent devices incorporating the materials produced by the subject method. The subject method for spark-processing can enhance the EL output, as compared with conventional spark-processed (sp) silicon. The enhancement of EL output can be due, at least in part, to increasing the light emitting area. The subject method can smooth the sp surface, so as to allow more complete coverage of the sp area with a continuous, semitransparent, conducting film. The smoothening of the sp surface can be accomplished by, for example, introducing into the spark plasma a volatile liquid, such as methanol, ethanol, acetone, in which particles can be suspended and/or in which a heavy ion salt is dissolved. The particles preferably float in the volatile liquid, rather than settle quickly. In a specific embodiment, silicon particles in the range of about 0.

Abstract: A circuit device manufacturing method is provided, wherein the adhesion of an overcoat resin, formed on a conductive wiring layer, to a sealing resin layer is improved by irradiating plasma onto the overcoat resin. A first conductive film 23A and a second conductive film 23B, which are laminated with an interlayer insulating layer 22 interposed in between, are formed. By selectively removing the first conductive film, a first conductive wiring layer 12A is formed and the first conductive wiring layer is covered with an overcoat resin 18. Overcoat resin 18 is irradiated with plasma to roughen its top surface. A sealing resin layer 17 is formed so as to cover the top surface of the roughened overcoat resin 18 and circuit elements 13.

Abstract: Methods for fabricating a contact of a semiconductor device are provided by patterning an interlayer dielectric of the semiconductor device to form a contact hole that exposes a silicon-based region of a first impurity type. The exposed silicon-based region is doped with a gas containing an element of the first impurity type and a contact plug is formed in the contact hole. Contact structure for a semiconductor device are also provided that include an interlayer dielectric of the semiconductor device having a contact hole formed therein that exposes a silicon-based region of a first impurity type. A delta-doped region of the first impurity type is provided in the exposed silicon-based region. A contact plug is provided in the contact hole and on the delta-doped region.

Abstract: A method for manufacturing a capacitor in a semiconductor device for securing capacitance without a merging phenomenon during a MPS grain growth process. The manufacturing step begins with a preparation of a substrate. The interlayer dielectric (ILD) layer is formed on the substrate and is etched to form conductive plug. Then, an etch barrier layer and a sacrifice insulating layer are formed on entire surface subsequently. A cylinder typed first electrode is formed over the conductive plug using the sacrifice insulating layer. Thereafter, first meta-stable poly silicon (MPS) grains are formed on inner wall of the first electrode except a bottom region thereof. However, second MPS grains with small sizes can be formed in the bottom region for increasing a storage area of the first electrode. Finally, a dielectric layer and a second electrode are formed on the first electrode subsequently.

Abstract: Method of etching a ferroelectric layer includes etching an upper electrode and partially through a ferroelectric layer. A dielectric material is subsequently deposited upon the upper electrode and the partially etched ferroelectric layer. A second etch step completely etches through the remaining portion of the ferroelectric layer and also etches lower electrodes. A random access memory apparatus is constructed that includes a first conductive layer, a dielectric layer disposed upon the first conductive layer, a second conductive layer disposed upon the dielectric layer, where such layers form a stack having a sidewall. Further, the sidewall has a protective dielectric film disposed thereon and extending from the second layer down to the dielectric layer.

Abstract: Provided is a method for manufacturing a semiconductor device including a plurality of different semiconductor elements with a transistor for fabricating the semiconductor device formed on a semiconductor substrate, an interlayer insulation film formed all over the upper part, and a hole trap site formed in the interlayer insulation film for preventing a mobile ion like H or moisture from penetrating, whereby it can be prevented that a leakage current increases abnormally where the voltage difference (Vgs) is lower than a threshold voltage.

Abstract: In a pretreatment process, a silicon oxide film (13) with nitrogen content is formed on a semiconductor substrate (10). In a segregation process executing heat treatment in an in-oxidiz-able gas atmosphere, a silicon nitride layer (14) segregates out at the interface of the silicon substrate (10) and the silicon oxide film (13). After this, the unnecessary silicon oxide film (13) on the silicon nitride layer (14) is removed, and a silicon oxide layer (15) is formed beneath the exposed silicon nitride layer (14) with oxygen passing through the exposed silicon nitride layer (14). Whereby, a gate electrode (16) is formed on the gate insulating film consisting of the silicon nitride layer (14) and the silicon oxide layer (15).

Abstract: The invention provides a method for forming spacers very productively. A method for manufacturing a semiconductor wafer includes forming spacers on a plurality of semiconductor chips arranged in a plane on a substrate, respectively. The steps of forming the multiple spacers are conducted collectively on the substrate.

Abstract: A method for fabricating low k and ultra-low k multilayer interconnect structures on a substrate includes: a set of interconnects separated laterally by air gaps; forming a support layer in the via level of a dual damascene structure that is only under the metal line; removing a sacrificial dielectric through a perforated bridge layer that connects the top surfaces of the interconnects laterally; performing multilevel extraction of a sacrificial layer; sealing the bridge in a controlled manner; and decreasing the effective dielectric constant of a membrane by perforating it using sub-optical lithography patterning techniques.

Abstract: Provided is a nitride semiconductor device with high reliability and high flexibility in design and manufacture of the device. The nitride semiconductor device comprises a seed crystal portion (11) formed on a sapphire substrate (10) and having a mask (12) on one side surface thereof, and a GaN layer (15) grown on the sapphire substrate (10) and the seed crystal portion (11) through epitaxial lateral overgrowth. The GaN layer (15) is grown only from an exposed side surface of the seed crystal portion (11) which is not covered with the mask (12), so the lateral growth of the GaN layer (15) is asymmetrically carried out. Thereby, a meeting portion (32) is formed in the vicinity of a boundary between the seed crystal portion (11) and the mask (12) in a thickness direction of the GaN layer (15).

Abstract: A technique for more efficiently forming conductive elements, such as conductive layers and electrodes, using chemical vapor deposition. A conductive precursor gas, such as a platinum precursor gas, having organic compounds to improve step coverage is introduced into a chemical vapor deposition chamber. A reactant is also introduced into the chamber that reacts with residue organic compounds on the conductive element so as to remove the organic compounds from the nucleating sites to thereby permit more efficient subsequent chemical vapor deposition of conductive elements.

Abstract: A contact collect is provided to prevent damage to the top surface of a semiconductor chip at the time of die bonding the semiconductor chip. A protection tape is pasted to the top surface of the semiconductor chip before die bonding of the semiconductor chip is executed by pressing the back surface (underside) of the semiconductor chip sucked and securely held by the contact collect against respective chip-mounting regions of a multi-wiring board. The contact collect is, for example, substantially cylidrical in outside shape, and a bottom part (suction head) thereof is made of soft synthetic rubber, etc. The protection tape pasted to the top surface of the semiconductor chip prevents the top surface of the semiconductor chip from directly contacting with the contact collect even at the time of vacuum suction by pressing the suction head of the contact collect against the top surface of the semiconductor chip.

Abstract: A method of fabricating a MOSFET device featuring a raised source/drain structure on a heavily doped source/drain region as well as on a portion of a lightly doped source/drain (LDD), region, after removal of an insulator spacer component, has been developed. After formation of an LDD region a composite insulator spacer, comprised of an underlying silicon oxide spacer component and an overlying silicon nitride spacer component, is formed on the sides of a gate structure. Formation of a heavily doped source/drain is followed by removal of the silicon nitride spacer resulting in recessing of, and damage formation to, the heavily doped source/drain region, as well as recessing of the gate structure. Removal of a horizontal component of the silicon oxide spacer component results in additional recessing of the heavily doped source/drain region, and of the gate structure.

Abstract: First of all, a semiconductor substrate is provided, and then a first/second wells with a first conductivity are formed therein so as to individually form a first part of the floating gate of single-level EEPROM and a low-voltage device thereon, wherein the first and the second wells are used to separate the high-voltage device, and the depth of the first well is the same as the second well. Furthermore, the high-voltage device and the second part of the floating gate of single-level EEPROM are individually formed on the semiconductor substrate between the first and the second wells, and the control gate of the floating gate of single-level EEPROM is formed in the third well located under the second part of the floating gate of single-level EEPROM, wherein the high-voltage device can be operated in the opposite electric field about 18V, such as ?6V˜12V, ?12V˜6V, ?9V˜9V etc.

Abstract: Methods of fabricating leadless packages are described that provide good solder joint reliability. In most respects, the packages are fabricated in a manner similar to current lead frame based leadless packaging techniques. However, at some point in the process, the contacts are provided with undercut regions that are left exposed during solder plating so that the solder plating also covers the exposed side and undercut segments of the contacts. When the resultant devices are soldered to an appropriate substrate (after singulation), each resulting solder joint includes a fillet that adheres very well to the undercut portion of contact. This provides a high quality solder joint that can be visually inspected from the side of the package.

Abstract: The invention provides a method of making silicon-on-insulator SOI substrates with nitride buried insulator layer by implantation of molecular deuterated ammonia ions ND3+, instead of implanting nitrogen ions (N+, or N2+) as is done in prior art nitride SOI processes. The resultant structure, after annealing, has a buried insulator with a defect density which is substantially lower than in prior art nitride SOI. The deuterated nitride SOI substrates allow much better heat dissipation than SOI with a silicon dioxide buried insulator. These substrates can be used for manufacturing of high speed and high power dissipation monolithic integrated circuits.

Abstract: The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a multi-layer hard mask. The multi-layer hard mask comprises a hard masking layer overlying an etch stop layer. The etch stop layer is substantially more selective than the overlying masking layer with respect to an etch employed to remove the bottom electrode diffusion barrier layer. Therefore during an etch of the capacitor stack, an etch of the bottom electrode diffusion barrier layer results in a substantially complete removal of the hard masking layer. However, due to the substantial selectivity (e.g., 10:1 or more) of the etch stop layer with respect to the overlying masking layer, the etch stop layer completely protects the underlying top electrode, thereby preventing exposure thereof.

Abstract: A polysilicon layer (30) is formed on a dielectric region (20). An optional metal silicide layer (50) can be formed on the polysilicon layer. A dielectric layer (60) is formed over the metal silicide layer and a conductive layer (70) formed over the dielectric layer. The formed layers are etched by a combination of multi-step dry and wet process to form high precision integrated circuit capacitors.