Abstract: A semiconductor device includes a first power supply line, a second power supply line, a first ground line, a switch circuit connected to the first and the second power supply line, and a switch control circuit connected to the first ground line and the first power supply line. The switch circuit includes a first and a second transistor of a first conductive type. A first gate electrode of the first transistor is connected to a second gate electrode of the second transistor. The switch control circuit includes a third transistor of a second conductive type, and a fourth transistor of a third conductive type. A third gate electrode of the third transistor is connected to a fourth gate electrode of the fourth transistor. A semiconductor device includes a signal line that electrically connects a connection point between the third and fourth transistor to the first and second gate electrode.

Abstract: The present disclosure relates to a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a first nitride semiconductor layer disposed on the substrate, a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a bandgap greater than that of the first nitride semiconductor layer. The semiconductor device further includes a first gate conductor disposed on a first region of the second nitride semiconductor layer, a passivation layer covering the first gate conductor, and a second gate conductor disposed on the passivation layer and on a second region of the second nitride semiconductor layer, wherein the first region is laterally spaced apart from the second region.

Abstract: A display panel, a method of manufacturing a display panel, and a display device are provided. The display panel includes: a substrate; a light-emitting device layer arranged on the substrate; a first thin film encapsulation layer including at least one organic layer; a color filter layer; a second thin film encapsulation layer including at least one organic layer; and an adhesive film layer arranged on at least one side of the color filter layer, wherein the adhesive film layer is in direct contact with the color filter layer, and the adhesive film layer and the color filter layer are stacked, and a material of the adhesive film layer has a viscosity greater than a viscosity of a material of the organic layer in each of the first thin film encapsulation layer and the second thin film encapsulation layer.

Abstract: The present application provides a semiconductor device, which includes a shallow trench isolation structure, located in a substrate, and comprises a first region and a second region alternately arranged. The width of the first region is greater than the width of the second region. A first filling layer and a second filling layer are sequentially arranged in the first region, and a first filling layer is arranged in the second region; wherein, in the first region, the height of the first filling layer is lower than the height of the second filling layer. The device provides an advantage that the saddle-shaped shallow trench isolation structure in the first region reduces the trapping centers during any interference from adjacent word line structures, and also reduces the overlap areas of adjacent word line structures formed subsequently, thereby reducing parasitic capacitance, curtailing leakage and improving the semiconductor device's performance.

Abstract: A method of forming a multi color resist structure includes providing a substrate including an underlayer material; forming a first organic planarizing layer on the substrate; forming a first anti reflecting layer on the first organic planarizing layer, forming and developing a first patterned resist on the first anti reflecting layer; forming a second organic planarizing layer on the first anti reflecting layer and on the first patterned resist; forming a second anti reflecting layer on the second organic planarizing layer and forming and developing the second patterned resist, wherein the first patterned resist is a non-chemically amplified resist (n-CAR) or metal resist and the second patterned resist is CAR organic resist.

Abstract: A display panel includes: a driving substrate, a plurality of first electrodes, a hole transport layer, an organic light emitting layer, a second electrode layer and a color film layer. The hole transport layer includes a first portion and a second portion, the first portion is disposed between adjacent ones of the plurality of first electrodes and is located on a surface of the driving substrate; the second portion is disposed on a surface of each of the first electrodes away from the driving substrate; a minimum distance between an upper surface of the first portion away from the driving substrate and the driving substrate is smaller than an minimum distance between an upper surface of the second portion away from the driving substrate and the driving substrate.

Abstract: The composite defect includes an extended defect and a basal plane dislocation. The extended defect includes a first region extending in a <11?20> direction from an origin located at a boundary between the silicon carbide substrate and the silicon carbide epitaxial film, and a second region extending along a <1?100> direction. The first region has a width in the <1?100> direction that increases from the origin toward the second region. The basal plane dislocation includes a third region continuous to the origin and extending along the <1?100> direction, and a fourth region extending along a direction intersecting the <1?100> direction. When an area of the main surface is a first area, and an area of a quadrangle circumscribed around the composite defect is a second area, a value obtained by dividing the second area by the first area is not more than 0.001.

Abstract: A semiconductor interconnect and an electrode for semiconductor devices may include a thin film including a multielement compound represented by Formula 1 and having a thickness equal to or less than about 50 nm, a grain size (A) to thickness (B) ratio (A/B) equal to or greater than about 1.2, and a resistivity equal to or less than about 200 ??·cm: Mn+1AXn??Formula 1 In Formula 1, M, A, X, and n are as described in the specification.

Abstract: A rotor assembly has a rotor hub having a unitary structure. The rotor assembly further includes a unitary crosshead having a first upper tab and a first lower tab located vertically below the first upper tab. The first upper tab and the first lower tab define a slot therebetween to accept a first pin of the first rotor blade. A second upper tab and a second lower tab located vertically below the second upper tab define a slot therebetween to accept a second pin of the second rotor blade. A first recess is provided between the first lower tab and the second lower tab so that the crosshead comprises no material directly between at least a portion of the first lower tab and the second lower tab along at least one straight path.

Abstract: Apparatus and methods for real time calibration of qubits in a quantum processor. For example, one embodiment of an apparatus comprises: a quantum processor comprising a plurality of qubits, each of the qubits having a state; a quantum controller to generate sequences of electromagnetic (EM) pulses to manipulate the states of the plurality of qubits based on a set of control parameters; a qubit measurement unit to measure one or more sensors associated with a corresponding one or more of the qubits of the plurality of qubits to produce one or more corresponding measured values; and a machine-learning engine to evaluate the one or more measured values in accordance with a machine-learning process to generate updated control parameters, wherein the quantum controller is to use the updated control parameters to generate subsequent sequences of EM pulses to manipulate the states of the plurality of qubits.

Abstract: An array substrate includes a base, a first conductive layer disposed at a side of the base, an insulating layer disposed at a side of the first conductive layer away from the base, and a second conductive layer disposed at a side of the insulating layer away from the first conductive layer. The insulating layer is provided with a first via hole exposing the first electrode of the first transistor and a second via hole exposing the first electrode of the second transistor. The second conductive layer includes a first conductive connection portion, and the first conductive connection portion connects the first electrode of the first transistor and the first electrode of the second transistor through the first via hole and the second via hole.

Abstract: A display device includes: a substrate; a metal layer disposed on the substrate; an insulating layer disposed on the metal layer; and a first light emitting diode including a first electrode disposed on the metal layer, wherein a via hole passes through the insulating layer, the first electrode electrically connects to the metal layer through the via hole, and an outline of the via hole includes an arc edge.

Abstract: The present application provides an array substrate and a manufacturing method thereof. The array substrate includes a substrate; an active layer comprising a channel region; a gate insulating layer; a gate corresponding to the channel region of the active layer; and a source and a drain disposed at opposite ends of the active layer, wherein the gate has a groove structure, the groove structure has an opening facing the active layer, and a region of the groove structure corresponding to the active layer is the channel region.

Abstract: There are provided a laser irradiation apparatus, a laser irradiation method, and a semiconductor device manufacturing method that reduce irradiation unevenness of a laser beam. A laser irradiation apparatus includes a waveform shaping device (20). The waveform shaping device (20) includes a laser beam source (11), a first waveform shaping unit (30) that shapes the pulse waveform of a pulse laser beam by applying a delay according to an optical path length difference between two light beams (L11 and L12) branched by a first beam splitter (31), a wave plate that changes the polarization state of the pulse laser beam from the first waveform shaping unit (30), and a second waveform shaping unit (40) that shapes the pulse waveform of the pulse laser beam by applying a delay according to an optical path length difference between two light beams (L15 and L16) branched by a second beam splitter (41).

Abstract: A hermetically sealed package includes: a base substrate and a cover substrate which define at least part of the package, the base substrate and the cover substrate being hermetically sealed to one another by at least one laser bonding line, the at least one laser bonding line having a height perpendicular to its bonding plane, at least the cover substrate including a toughened layer at its surface, at least on a side opposite the at least one laser bonding line; and at least one functional area enclosed in the package.

Abstract: A method for manufacturing a semiconductor structure includes: a substrate is provided, in which the substrate is provided with a peripheral area and an array area; an insulation layer is formed on the substrate; a first mask layer with a first mask pattern is formed on the insulation layer; the insulation layer is etched by taking the first mask layer as a mask, to form a contact hole in the array area; a first electrode layer is formed; a second mask layer with a second mask pattern is formed, in which the second mask layer is arranged on the first electrode layer; and the first electrode layer and the first mask layer are etched by taking the second mask layer as a mask until the insulation layer in the array area is exposed, in which a remaining portion of the first electrode layer forms a lower electrode layer.

Abstract: The chuck for supporting a target substrate for a display device, the chuck includes: a base having a first surface to support an object and a second surface opposite the first surface, the first surface including a first area and a second area; and indentations formed in the second area and recessed from the first area in a thickness direction of the base. The indentations include a first indentation extending in a first direction and a second indentation extending in a second direction intersecting the first direction.

Abstract: A capacitive biosensor is provided. The capacitive biosensor includes: a transistor, an interconnect structure on the transistor, and a passivation layer on the interconnect structure. The interconnect structure includes a first metal structure on the transistor, a second metal structure on the first metal structure, and a third metal structure on the second metal structure. The third metal structure includes a first conductive layer, a second conductive layer, and a third conductive layer that are sequentially stacked. The passivation has an opening exposing a portion of the third metal structure. The capacitive biosensor further includes a sensing region on the interconnect structure. The sensing region includes a first sensing electrode and a second sensing electrode. The first sensing electrode is formed of the third conductive layer, and the second sensing electrode is disposed on the passivation layer.

Abstract: Provided is a semiconductor device including a buffer region. Provided is a semiconductor device including: semiconductor substrate of a first conductivity type; a drift layer of the first conductivity type provided in the semiconductor substrate; and a buffer region of the first conductivity type provided in the drift layer, the buffer region having a plurality of peaks of a doping concentration, wherein the buffer region has: a first peak which has a predetermined doping concentration, and is provided the closest to a back surface of the semiconductor substrate among the plurality of peaks; and a high-concentration peak which has a higher doping concentration than the first peak, and is provided closer to an upper surface of the semiconductor substrate than the first peak is.

Abstract: A display device includes a first electrode disposed on a substrate, a pixel defining layer exposing at least a part of the first electrode and disposed on the substrate, a light emitting layer disposed on the first electrode, a second electrode disposed on the light emitting layer, and an encapsulation layer disposed on the second electrode, wherein the pixel defining layer includes an overlapping area overlapping the first electrode and a non-overlapping area not overlapping the first electrode, the overlapping area includes a first overlapping area spaced apart from the first electrode and facing the first electrode, and the encapsulation layer is at least partially disposed in a space between the first electrode and the pixel defining layer in the first overlapping area.