Patents Examined by Michael Lebentritt
  • Patent number: 11915935
    Abstract: The invention relates to a method for producing a semiconductor component comprising performing a plasma treatment of an exposed surface of a semiconductor material with halogens, and carrying out a diffusion method with dopants on the exposed surface.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: February 27, 2024
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Andreas Biebersdorf, Stefan Illek, Christoph Klemp, Ines Pietzonka, Petrus Sundgren
  • Patent number: 11917884
    Abstract: A display apparatus includes a display panel; and a light control member disposed on the display panel. The light control member includes a plurality of partition walls spaced apart from each other, and a plurality of light control units each disposed between any two of the plurality of partition walls, and at least one of the plurality of light control units includes a first region containing organic monomers and an inorganic material and a second region containing the inorganic material dispersed in an organic polymer, thereby improving display quality and reliability of the display apparatus.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: February 27, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Youngsoo Kwon, Soodong Kim, Jinwon Kim, Hye-Jin Paek, Taeyoung Song, Kiheon Lee
  • Patent number: 11905222
    Abstract: An environmental barrier coating, comprising a substrate containing silicon; an environmental barrier layer applied to said substrate; said environmental barrier layer comprising a rare earth composition.
    Type: Grant
    Filed: December 2, 2022
    Date of Patent: February 20, 2024
    Assignee: RTX Corporation
    Inventors: Elisa M Zaleski, Richard Wesley Jackson, Xia Tang
  • Patent number: 11908688
    Abstract: A method for manufacturing a nitride semiconductor substrate, including: a step of preparing a base substrate; a step of forming a mask layer having a plurality of openings on the main surface of the base substrate; a first step of growing a first layer whose surface is composed only of inclined interfaces; and a second step of epitaxially growing a single crystal of a group III nitride semiconductor on the first layer, making the inclined interfaces disappear, and growing a second layer having a mirror surface, wherein in the first step, at least one valley and a plurality of tops are formed at an upper side of each of the plurality of openings of the mask layer by forming a plurality of concaves on a top surface of the single crystal and making the (0001) plane disappear.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: February 20, 2024
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventor: Takehiro Yoshida
  • Patent number: 11910638
    Abstract: A display panel and a manufacturing method thereof are provided. The display panel includes an array substrate, a light emitting device layer, and an encapsulation layer. The encapsulation layer includes at least one first adhesive layer, and an orthographic projection of the at least one first adhesive layer on the array substrate is positioned in the array substrate.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: February 20, 2024
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Tianfu Guo, Hsianglun Hsu
  • Patent number: 11910667
    Abstract: A display apparatus includes a substrate including a display area and a peripheral area disposed outside the display area, a transistor disposed in the display area on the substrate, a first pad part disposed in the peripheral area on the substrate, a second pad part disposed in the peripheral area on the substrate and spaced apart from the first pad part, a first pad disposed in the second pad part, a second pad disposed in the second pad part and spaced apart from the first pad and a passivation layer including a plurality of grooves defined between the first pad and the second pad and a protrusion disposed between two adjacent grooves among the grooves.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: February 20, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jaewon Cho, Wonmi Hwang, Geurim Lee, Changwon Jeong
  • Patent number: 11908708
    Abstract: A method includes bonding a package component to a composite carrier. The composite carrier includes a base carrier and an absorption layer, and the absorption layer is between the base carrier and the package component. A laser beam is projected onto the composite carrier. The laser beam penetrates through the base carrier to ablate the absorption layer. The base carrier may then be separated from the package component.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Huicheng Chang, Jyh-Cherng Sheu, Chen-Fong Tsai, Yun Chen Teng, Han-De Chen, Yee-Chia Yeo
  • Patent number: 11901246
    Abstract: Provided is a display panel, including a through hole, an isolation area, and a display area. The isolation area is around the through hole. The isolation area is between the through hole and the display area. The isolation area includes at least two graphic marks for detecting the hole accuracy of the through hole. The at least two graphic marks are spaced apart from each other around the through holes. Graphic marks are arranged in an isolation area of a display panel. The isolation area is between a through hole and a display area. That is, the graphic marks are around the through hole.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: February 13, 2024
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhiwen Chu, Xiangdan Dong, Yulong Wei
  • Patent number: 11903207
    Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.
    Type: Grant
    Filed: May 20, 2022
    Date of Patent: February 13, 2024
    Assignee: Kioxia Corporation
    Inventors: Masaru Kito, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
  • Patent number: 11903205
    Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.
    Type: Grant
    Filed: May 13, 2022
    Date of Patent: February 13, 2024
    Assignee: Kioxia Corporation
    Inventors: Masaru Kito, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
  • Patent number: 11895863
    Abstract: A display panel, a manufacturing method and a display device are provided. The display panel includes a substrate having a display area and a non-display area; a planarization layer covering the display area and the non-display area of the substrate; an organic light emitting element located in the display area and located at a side of the planarization layer away from the substrate; an encapsulation structure including a first inorganic layer, an organic layer and a second inorganic layer which are sequentially stacked, where the first inorganic layer and the second inorganic layer extend into a non-display area, and the first inorganic layer is arranged close to the planarization layer; and/or, a part of the planarization layer located in the non-display area is provided with a groove, and the groove is filled with a flexible water-oxidation resistant material.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: February 6, 2024
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Heng Yang, Wei Li, Yanbo Zeng, Yinglong Huang
  • Patent number: 11885336
    Abstract: A blower may include a first case and a second case provided above the first case and having a first tower and a second tower that have a passage therebetween. A display assembly is received in the second case at a position that does not interfere with air flowing in the passage. An inner surface of the second tower and an outer surface of a diffuser define a space in which the display assembly is received.
    Type: Grant
    Filed: December 1, 2022
    Date of Patent: January 30, 2024
    Assignee: LG ELECTRONICS INC.
    Inventors: Hosik Jang, Kibbum Park, Seungho Baek, Hyungho Park, Hoojin Kim, Haein Jung, Jaehyuk Jung, Yongmin Kim, Chiyoung Choi
  • Patent number: 11887911
    Abstract: A semiconductor storage device includes a housing, an interface substrate attached to the housing, an insulating substrate in the housing, a first flexible substrate connecting the insulating substrate and the interface substrate, a first integrated circuit on a first surface of the insulating substrate, and a first heat conductor arranged on a second surface of the insulating substrate that is opposite to the first surface, and contacting a first inner surface of the housing.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: January 30, 2024
    Assignee: Kioxia Corporation
    Inventors: Daigo Suzuki, Kosuke Awaga
  • Patent number: 11879423
    Abstract: The present invention provides a turbine sub-runner that is positioned to be within the vortex zone of a turbine wicket gates (zone “S-R”, FIG. 1). The sub-runner includes at least two sub-runner blades, configured to monitor the relative flow of the vortex created by the wicket gates. A control mechanism is connected to the sub-runner shaft via gear and threaded interface, and is capable of transferring the relative (vs main-runner) rotational energy of the sub-runner into angular movement of the main runner blades. As the sub-runner interacts with the changing conditions of the main vortex within the zone “S-R”, it will act to automatically regulate, adjust, and control the angle of the main runner blades to optimize the performance of the turbine. The sub-runner uses the energy of the vortex existing in the zone “S-R” to perform the monitoring, regulation, adjustment and control of the main runner through regulating angular position of main runner blades.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: January 23, 2024
    Assignee: COMPOSITE HYDRAULIC TURBINE OTTAWA INC.
    Inventor: Jacek Swiderski
  • Patent number: 11876129
    Abstract: Embodiments of the present application disclose a semiconductor structure and a manufacturing method for the semiconductor structure, which solve problems of complicated manufacturing process and poor stability and reliability of existing semiconductor structures. The semiconductor structure includes: a substrate; a channel layer and a barrier layer sequentially superimposed on the substrate, wherein the channel layer and the barrier layer are made of GaN-based materials and an upper surface of the barrier layer is Ga-face; and a p-type GaN-based semiconductor layer formed in a gate region of the barrier layer. An upper surface of the p-type GaN-based semiconductor layer is N-face.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: January 16, 2024
    Assignee: ENKRIS SEMICONDUCTOR, INC.
    Inventor: Kai Cheng
  • Patent number: 11870411
    Abstract: A process for fabricating a substrate for a radiofrequency device by joining a piezoelectric layer to a carrier substrate by way of an electrically insulating layer, the piezoelectric layer having a rough surface at its interface with the electrically insulating layer, the process being characterized in that it comprises the following steps: —providing a piezoelectric substrate having a rough surface for reflecting a radiofrequency wave, —depositing a dielectric layer on the rough surface of the piezoelectric substrate, —providing a carrier substrate, —depositing a photo-polymerizable adhesive layer on the carrier substrate, —bonding the piezoelectric substrate to the carrier substrate by way of the dielectric layer and of the adhesive layer, in order to form an assembled substrate, —irradiating the assembled substrate with a light flux in order to polymerize the adhesive layer, the adhesive layer and the dielectric layer together forming the electrically insulating layer.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: January 9, 2024
    Assignee: SOITEC
    Inventors: Djamel Belhachemi, Thierry Barge
  • Patent number: 11864415
    Abstract: Provided are a display panel and a preparation method thereof, and a display apparatus. The display panel includes a first display region, and the first display region includes multiple sub-display regions and a first light transmittance region located between adjacent sub-display regions. Each first sub-display region of the multiple sub-display regions includes a first light-emitting element and a first filter unit disposed in a first light-emergence direction of the first light-emitting element. Each second sub-display region in the multiple sub-display regions includes a first collimating light extraction element disposed in a second light-emergence direction of the first light-emitting element and a second filter unit disposed in a light-emergence direction of the first collimating light extraction element.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: January 2, 2024
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Wenqu Liu, Feng Zhang, Qi Yao, Zhao Cui, Xiaoxin Song, Zhijun Lv, Dongfei Hou, Detian Meng, Liwen Dong, Libo Wang, Yang Yue, Haitao Huang, Chuanxiang Xu
  • Patent number: 11856831
    Abstract: The present disclosure provides a color filter substrate and a method for manufacturing the same, and a display device, and the color filter substrate includes a base substrate, a black matrix and a color filter layer located on the base substrate, a quantum dot layer located on a side of the color filter layer away from the base substrate, a barrier layer located on a side of the black matrix away from the base substrate, and a first inorganic layer, and the first inorganic layer at least includes: a first portion located between the color filter layer and the quantum dot layer; a second portion located on the base substrate and between the quantum dot layer and the barrier layer; and a third portion located on a side of the barrier layer away from the base substrate.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: December 26, 2023
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Kai Sui, Xiaolei Zhang, Zhongyuan Sun, Yuan Jia, Dapeng Xue, Lubin Shi
  • Patent number: 11854893
    Abstract: A method of manufacturing a semiconductor package, includes forming a mask layer on a wafer, the wafer including a semiconductor substrate and an insulating layer; forming a groove in the semiconductor substrate by performing a first laser grooving process; expanding an opening of the mask layer opened by the first laser grooving process by performing a second laser grooving process; exposing a portion of the insulating layer by removing a portion of the mask layer; and cutting the semiconductor substrate while removing the portion of the insulating layer exposed during the exposing by performing a dicing process.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: December 26, 2023
    Inventors: Junyun Kweon, Jumyong Park, Solji Song, Dongjoon Oh, Chungsun Lee, Hyunsu Hwang
  • Patent number: 11856834
    Abstract: The present disclosure provides a display substrate, a method for preparing the same, and a display device. The display substrate includes an insulating pattern whose surface layer is composed of a hydrophobic fluorine-containing material, so the organic ink used to prepare a light emitting layer does not overflow outside a pixel area. The method for preparing the display substrate includes: forming a rheological insulating material layer on the base substrate; curing the rheological insulating material layer, and patterning the cured insulating material layer to obtain an insulating pattern; heating the insulating pattern, to gather the hydrophobic insulating structure on a surface of the insulating pattern away from the base substrate; heating the gathered hydrophobic insulating structure to melt it, and then cooling the molten hydrophobic insulating structure to form a metal pattern on the surface of the insulating pattern.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: December 26, 2023
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Ying Cui