Abstract: A micro-LED chip includes multiple micro-LEDs. At least one micro-LED of the multiple micro-LEDs includes: a first type conductive layer; a second type conductive layer stacked on the first type conductive layer; and a light emitting layer formed between the first type conductive layer and the second type conductive layer. The light emitting layer is continuously formed on the whole micro-LED chip, the multiple micro-LEDs sharing the light emitting layer. The micro-LED chip further includes: a top spacer formed on a top surface of the light emitting layer; a bottom spacer formed on a bottom surface of the light emitting layer; and an isolation structure formed between adjacent micro-LEDs.

Abstract: A system for the treatment of a region of an object adjacent to a substrate. The system includes a source of an incident laser beam delivering a focused laser beam. The wavelength of the incident laser beam is greater than the sum of 500 nm and of the wavelength associated with the bandgap of the material forming the substrate and smaller than the sum of 2,500 nm and of this wavelength. The system includes an optical device associating a digital aperture greater than 0.3 and means for correcting the spherical aberrations appearing during the crossing of the substrate for a given thickness of the substrate and a given distance between the substrate and the optical device. The processing being performed on the region through the substrate, and including the physical, chemical, or physico-chemical modification or the ablation of said region.

Abstract: A flexible photovoltaic (PV) cell having enhanced properties of mechanical impact absorption, includes: a semiconductor wafer that is freestanding and carrier-less; having a thickness, and having a first surface, and a having second surface that is opposite to that first surface; and non-transcending gaps within the semiconductor wafer. Each non-transcending gap penetrates from the first surface towards the second surface, but reaches to a depth of between 50 to 99 percent of the thickness of the semiconductor wafer, and does not reach said second surface. Each non-transcending gap does not entirely penetrate through an entirety of the thickness of the semiconductor wafer. The semiconductor wafer maintains between 1 to 50 percent of the thickness of the semiconductor wafer as an intact and non-penetrated thin layer of semiconductor wafer that remains intact and non-penetrated by the non-transcending gaps.

Abstract: Provided is a semiconductor device including: a semiconductor substrate provided with an active portion and an edge termination structure portion surrounding the active portion; an interlayer dielectric film provided above the semiconductor substrate; a protective film provided above the interlayer dielectric film; and a protruding portion provided farther from the active portion than the edge termination structure portion and protruding further than the interlayer dielectric film. The protruding portion is not covered with the protective film. The protective film is provided closer to the active portion than the protruding portion.

Abstract: A display device that can easily have high resolution is provided. A display device having both high display quality and high resolution is provided. A display device with high contrast is provided. A first EL film is deposited in contact with a top surface and a side surface of each of a first pixel electrode and a second pixel electrode each having a tapered shape. A first sacrificial film is formed to cover the first EL film. The first sacrificial film and the first EL film are etched to expose the second pixel electrode and form a first EL layer over the first pixel electrode and a first sacrificial layer over the first EL layer, and then, the first sacrificial layer is removed. The first EL film and the second EL film are etched by dry etching. The first sacrificial layer is removed by wet etching.

Abstract: A micro-LED chip includes multiple micro-LEDs. At least one micro-LED of the multiple micro-LEDs includes: a first type conductive layer; a second type conductive layer stacked on the first type conductive layer; and a light emitting layer formed between the first type conductive layer and the second type conductive layer. The light emitting layer is continuously formed on the whole micro-LED chip, the multiple micro-LEDs sharing the light emitting layer. The micro-LED chip further includes: a top spacer formed on a top surface of the light emitting layer; a bottom spacer formed on a bottom surface of the light emitting layer; and an isolation structure formed between adjacent micro-LEDs.

Abstract: A micro-LED chip includes multiple micro-LEDs. At least one micro-LED of the multiple micro-LEDs includes: a first type conductive layer; a second type conductive layer stacked on the first type conductive layer; and a light emitting layer formed between the first type conductive layer and the second type conductive layer. The light emitting layer is continuously formed on the whole chip, the multiple micro-LEDs sharing the light emitting layer. An isolation structure is formed between adjacent micro-LEDs, at least a portion of the isolation structure being formed in the light emitting layer. A top surface of the isolation structure is aligned with a top of the light emitting layer, and a bottom surface of the isolation structure is under the light emitting layer.

Abstract: An improved method of forming conductive features and a semiconductor device formed by the same are disclosed. In an embodiment, a method includes forming a metal line extending through a first dielectric layer, the metal line being electrically coupled to a transistor; selectively depositing a sacrificial material over the metal line; selectively depositing a first dielectric material over the first dielectric layer and adjacent to the sacrificial material; selectively depositing a second dielectric material over the first dielectric material; removing the sacrificial material to form a first recess exposing the metal line; and forming a metal via in the first recess and electrically coupled to the metal line.

Abstract: A display substrate and a display panel are provided. The display substrate has an opening region, a transition region surrounding the opening region, and a display region surrounding the transition region; the display substrate includes: a base plate, post spacers and dam structures on the base plate and in the transition region and surrounding the opening region; the post spacers include a first post spacer on a side of the dam structures proximal to the display region; an organic light emitting diode, a first encapsulation layer, a second encapsulation layer and a third encapsulation layer are sequentially arranged on the base plate, the organic light emitting diode is in the display region, and orthographic projections of the first encapsulation layer and the third encapsulation layer on the base plate at least cover the display region and the transition region.

Abstract: A display device includes a first pixel and a second pixel. A light emitting element and a pixel circuit of the second pixel are in a second area. The first pixel includes a silicon transistor and an oxide transistor in the second area. The first pixel includes a connection line that electrically connects one of the silicon transistor and the oxide transistor to a light emitting element in a first area. The connection line is on the same layer as the oxide semiconductor pattern and includes a transparent conductive oxide.

Abstract: The present disclosure provides new processes and methods to pre-treat metal surfaces in the back end of line (BEOL) fabrication of integrated circuits (ICs). More specifically, the present disclosure provides selective, self-limiting processes and methods for stripping native oxide surface layers that may form on exposed metal surfaces during processing of ICs. The processes and methods disclosed herein utilize the fundamental concepts of metal complexation to provide a novel solution, which enables native oxide surface layers to be selectively removed from exposed metal films in a self-limiting manner. In particular, the disclosed processes and methods use complexing agents (e.g., ligands) to selectively dissolve native oxide surface layers, without significantly etching or removing the underlying metal film.

Abstract: A micro-LED chip includes multiple micro-LEDs. At least one micro-LED of the multiple micro-LEDs includes: a first type conductive layer; a second type conductive layer stacked on the first type conductive layer; and a light emitting layer formed between the first type conductive layer and the second type conductive layer. The light emitting layer is continuously formed on the whole micro-LED chip, and the multiple micro-LEDs sharing the light emitting layer. An isolation structure is formed between adjacent micro-LEDs, at least a portion of the isolation structure being formed in the light emitting layer. A bottom surface of the isolation structure is aligned with a bottom of the light emitting layer, and a top surface of the isolation structure is aligned with a top surface of the light emitting layer.

Abstract: A micro-LED chip includes multiple micro-LEDs. At least one micro-LED of the multiple micro-LEDs includes: a first type conductive layer; a second type conductive layer stacked on the first type conductive layer; and a light emitting layer formed between the first type conductive layer and the second type conductive layer. The light emitting layer is continuously formed on the whole micro-LED chip, the multiple micro-LEDs sharing the light emitting layer.

Abstract: A high-electron-mobility transistor comprises a semiconductor body comprising a barrier region and a channel region that forms a heterojunction with the barrier region such that a two-dimensional charge carrier gas channel is disposed in the channel region, source and drain electrodes disposed on the semiconductor body and laterally spaced apart from one another, a gate structure disposed on the semiconductor body and laterally between the source and drain electrodes, the gate structure being configured to control a conduction state of two-dimensional charge carrier gas, and a first dielectric region that is disposed along the upper surface of the semiconductor body in a lateral region that is between the gate structure and the drain electrode, wherein the first dielectric region comprises aluminum and oxide, and wherein first dielectric region comprises a first end that faces and is laterally spaced apart from the gate structure.

Abstract: A gas turbine engine includes a fan having a plurality of fan blades, a turbomachine operably coupled to the fan for driving the fan, the turbomachine including a compressor section, a combustion section, and a turbine section in serial flow order and together defining a core air flowpath, a nacelle surrounding and at least partially enclosing the fan, the nacelle defining a longitudinal axis, and an inlet pre-swirl feature located upstream of the plurality of fan blades, the inlet pre-swirl feature attached to or integrated into the nacelle, wherein the inlet pre-swirl feature is transitionable between a first angle with respect to the longitudinal axis of the nacelle and a second angle with respect to the longitudinal axis of the nacelle.

Abstract: A micro-LED chip includes multiple micro-LEDs. At least one micro-LED of the multiple micro-LEDs includes: a first type conductive layer; a second type conductive layer stacked on the first type conductive layer; and a light emitting layer formed between the first type conductive layer and the second type conductive layer. The light emitting layer extends along a horizontal level from a top edge of the first type conductive layer and a bottom edge of the second type conductive layer. The micro-LED chip further includes a metal layer formed on a portion of the light emitting layer that extends from the second type conductive layer.

Abstract: A non-volatile memory device includes at least one memory cell, and the at least one memory cell includes a substrate, a stacked structure, a tunneling dielectric layer, a floating gate, a control gate structure, and an erase gate structure. The stacked structure is disposed on the substrate, and includes a gate dielectric layer, an assist gate, and an insulation layer stacked in order. The tunneling dielectric layer is disposed on the substrate at one side of the stacked structure. The floating gate is disposed on the tunneling dielectric layer and includes an uppermost edge and a curved sidewall. The control gate structure covers the curved sidewall of the floating gate. The erase gate structure covers the floating gate and the control gate structure, and the uppermost edge of the floating gate is embedded in the erase gate structure.

Abstract: The purpose of the present invention is to provide a novel method and apparatus of manufacturing a semiconductor substrate. Achieved are a method of manufacturing a semiconductor substrate and a manufacturing apparatus therefor, the method comprising: an installation step for installing a plurality of objects to be processed having semiconductor substrates in a stack; and a heating step for heating each of the plurality of objects to be processed such that a temperature gradient is formed in the thickness direction of the semiconductor substrate.

Abstract: A micro-LED chip includes multiple micro-LEDs. At least one micro-LED of the multiple micro-LEDs includes: a first type conductive layer; a second type conductive layer stacked on the first type conductive layer; and a light emitting layer formed between the first type conductive layer and the second type conductive layer. The light emitting layer is continuously formed on the whole micro-LED chip, the multiple micro-LEDs sharing the light emitting layer. The micro-LED chip further includes: a top spacer formed on a top surface of the light emitting layer; a bottom spacer formed on a bottom surface of the light emitting layer; and an isolation structure formed between adjacent micro-LEDs.

Abstract: An insulating film is formed on a semiconductor substrate, and a silicon film is formed on the insulating film. The silicon film and the insulating film in a transistor forming region are removed, and the silicon film and the insulating film in a transistor forming region are left. An insulating film is formed on the semiconductor substrate in the transistor forming region. A Hf-containing film is formed on the insulating film and the silicon film, and a silicon film is formed on the Hf-containing film. Then, a gate electrode is formed by patterning the silicon film, and a gate electrode is formed by patterning the silicon film. A gate insulating film under the gate electrode is formed by the insulating film, and a gate insulating film under the gate electrode is formed by the insulating film and the Hf-containing film.