Abstract: Embodiments relate to dynamic management of a transaction retry indication. One aspect is a system that includes a transactional facility configured to support transactions that effectively delay committing stores to memory or results to an architectural state until transaction completion, and a processor configured to identify a transaction abort reason associated with an aborted transaction of an initiating program. Transaction success and transaction abort history are tracked. Based on determining by the processor that the transaction abort reason was caused by the initiating program, a retry indication is assigned based on a static mapping of the transaction abort reason. Based on determining by the processor that the transaction abort reason was not caused by the initiating program, the retry indication is assigned based on a retry process using the transaction abort reason, the transaction abort history, and a current processor configuration.

Abstract: Sequential fetch requests from a set of fetch requests are combined into longer coalesced requests that match the width of a system memory interface in order to improve memory access efficiency for reading the data specified by the fetch requests. The fetch requests may be of different classes and each data class is coalesced separately, even when intervening fetch requests are of a different class. Data read from memory is ordered according to the order of the set of fetch requests to produce an instruction stream that includes the fetch requests for the different classes.

Abstract: A method and load and store buffer for issuing a load instruction to a data cache. The method includes determining whether there are any unresolved store instructions in the store buffer that are older than the load instruction. If there is at least one unresolved store instruction in the store buffer older than the load instruction, it is determined whether the oldest unresolved store instruction in the store buffer is within a speculation window for the load instruction. If the oldest unresolved store instruction is within the speculation window for the load instruction, the load instruction is speculatively issued to the data cache. Otherwise, the load instruction is stalled until any unresolved store instructions outside the speculation window are resolved. The speculation window is a short window that defines a number of instructions or store instructions that immediately precede the load instruction.

Abstract: Task specific diagnostic controls are provided to facilitate the debugging of certain types of abort conditions. The diagnostic controls may be set to cause transactions to be selectively aborted, allowing a transaction to drive its abort handler routine for testing purposes. The controls include, for instance, a transaction diagnostic scope and a transaction diagnostic control. The transaction diagnostic scope indicates when the transaction diagnostic control is to be applied, and the transaction diagnostic control indicates whether transactions are to selectively aborted.

Abstract: Task specific diagnostic controls are provided to facilitate the debugging of certain types of abort conditions. The diagnostic controls may be set to cause transactions to be selectively aborted, allowing a transaction to drive its abort handler routine for testing purposes. The controls include, for instance, a transaction diagnostic scope and a transaction diagnostic control. The transaction diagnostic scope indicates when the transaction diagnostic control is to be applied, and the transaction diagnostic control indicates whether transactions are to selectively aborted.

Abstract: Embodiments relate to asynchronous lookahead hierarchical branch prediction. An aspect includes a computer-implemented method for asynchronous lookahead hierarchical branch prediction using a second-level branch target buffer. The method includes receiving a search request to locate branch prediction information associated with a search address. The method further includes searching, by a processing circuit, for an entry corresponding to the search request in a first-level branch target buffer. The method also includes, based on failing to locate a matching entry in the first-level branch target buffer corresponding to the search request, initiating, by the processing circuit, a secondary search to locate entries in the second-level branch target buffer having a memory region corresponding to the search request. The method additionally includes, based on locating the entries in the second-level branch target buffer, performing a bulk transfer of the entries from the second-level branch target buffer.

Abstract: A TRANSACTION BEGIN instruction begins execution of a transaction and includes a general register save mask having bits, that when set, indicate registers to be saved in the event the transaction is aborted. At the beginning of the transaction, contents of the registers are saved in memory not accessible to the program, and if the transaction is aborted, the saved contents are copied to the registers.

Abstract: A TRANSACTION BEGIN instruction begins execution of a transaction and includes a general register save mask having bits, that when set, indicate registers to be saved in the event the transaction is aborted. At the beginning of the transaction, contents of the registers are saved in memory not accessible to the program, and if the transaction is aborted, the saved contents are copied to the registers.

Abstract: Embodiments relate to intra-instructional transaction abort handling. An aspect includes using an emulation routine to execute an instruction within a transaction. The instruction includes at least one unit of operation. The transaction effectively delays committing stores to memory until the transaction has completed successfully. After receiving an abort indication, emulation of the instruction is terminated prior to completing the execution of the instruction. The instruction is terminated after the emulation routine completes any previously initiated unit of operation of the instruction.

Abstract: Embodiments relate to implementing processor management of transactions. An aspect includes receiving an instruction from a thread. The instruction includes an instruction type, and executes within a transaction. The transaction effectively delays committing stores to memory until the transaction has completed. A processor manages transaction nesting for the instruction based on the instruction type of the instruction. The transaction nesting includes a maximum processor capacity. The transaction nesting management performs enables executing a sequence of nested transactions within a transaction, supports multiple nested transactions in a processor pipeline, or generates and maintains a set of effective controls for controlling a pipeline. The processor prevents the transaction nesting from exceeding the maximum processor capacity.

Abstract: Embodiments relate to asynchronous lookahead hierarchical branch prediction. An aspect includes a system for asynchronous lookahead hierarchical branch prediction. The system includes a first-level branch target buffer and a second-level branch target buffer coupled to a processing circuit. The processing circuit is configured to perform a method. The method includes receiving a search request to locate branch prediction information associated with a search address, and searching for an entry corresponding to the search request in the first-level branch target buffer. Based on failing to locate a matching entry in the first-level branch target buffer corresponding to the search request, a secondary search is initiated to locate entries in the second-level branch target buffer having a memory region corresponding to the search request. Based on locating the entries in the second-level branch target buffer, a bulk transfer of the entries is performed from the second-level branch target buffer.

Abstract: Embodiments relate to intra-instructional transaction abort handling. An aspect includes using an emulation routine to execute an instruction within a transaction. The instruction includes at least one unit of operation. The transaction effectively delays committing stores to memory until the transaction has completed successfully. After receiving an abort indication, emulation of the instruction is terminated prior to completing the execution of the instruction. The instruction is terminated after the emulation routine completes any previously initiated unit of operation of the instruction.

Abstract: A processor includes a loop counter that is reset to 0 when a loop instruction for executing a process in a loop from a loop start address to a loop end address is issued, a data memory that receives data that is used for executing a process in the loop, in which the data is transferred from outside, a calculator that uses the data transferred to the data memory to execute the process in the loop, a data counter that increments the loop counter by 1 every time a certain amount of data that is used for executing a process in the loop is transferred from outside to a data memory, and a loop controller that decrements the loop counter by 1 and causes the calculator to execute the process in the loop when a loop count value of the loop counter is not 0.

Abstract: Embodiments relate to second-level branch target buffer bulk transfer filtering. An aspect includes a system for second-level branch target buffer bulk transfer filtering. The system includes a first-level branch target buffer and a second-level branch target buffer coupled to a processing circuit. The processing circuit is configured to perform a method. The method includes receiving branch target buffer miss indicators, receiving instruction cache miss indicators, and recording information about the branch target buffer miss indicators and the instruction cache miss indicators in search trackers. Based on detecting, by the processing circuit, a search tracker representing a correlated pair of the branch target buffer miss indicators and the instruction cache miss indicators, the search tracker is activated by the processing circuit to perform a bulk transfer from the second-level branch target buffer to the first-level branch target buffer.

Abstract: A system for managing configuration of a storage network having multiple storage resources is disclosed. The system uses a storage management policy to set parameters for detecting storage resource problems in the storage network. The system monitors the storage resources in the storage network based on the storage management policy. Based on the monitoring, the system detects limited storage resource conditions, and identifies one or more potential solutions to the condition. After identifying potential solutions, the system simulates effects on the storage resources of implementing individual solutions. Based on the simulations, the system then implements one or more selected solutions. These solutions may be selected automatically or by a user.

Abstract: A vector slot processor that is capable of supporting multiple signal processing operations for multiple demodulation standards is provided. The vector slot processor includes a plurality of micro execution slot (MES) that performs the multiple signal processing operations on the high speed streaming inputs. Each of the MES includes one or more n-way signal registers that receive the high speed streaming inputs, one or more n-way coefficient registers that store filter coefficients for the multiple signal processing, and one or more n-way Multiply and Accumulate (MAC) units that receive the high speed streaming inputs from the one or more n-way signal registers and filter coefficients from one or more n-way coefficient registers. The one or more n-way MAC units perform a vertical MAC operation and a horizontal multiply and add operation on the high speed streaming inputs.