Abstract: Input/output (I/O) clock phase adjustment circuitry for use with I/O buffer circuitry of an integrated circuit chip. In one embodiment, an integrated circuit chip includes a phase adjustment circuit coupled to receive a system clock. The phase adjustment circuit generates an I/O clock coupled to be received by an I/O buffer circuit of an integrated circuit chip for I/O data transfers in a system. The phase adjustment circuit includes a phase locked loop (PLL) circuit coupled to receive the system clock through a first delay circuit. The I/O clock generated by the PLL circuit is received through a second delay circuit at a feedback clock input of the PLL circuit. The first and second delay circuits are used to control the phase of the I/O clock generated by the PLL circuit relative to the system clock. In one embodiment, a third delay circuit is included in an I/O data path of the I/O buffer circuit of the integrated circuit.

Abstract: A method and structure for performing a delayed counter increment is provided. The method and structure allows a counter decision to be modified based upon what the computer system hardware does with the data packet. Subsequent to the generation of a counter command, the processing of the data packet may change: for example, the data packet may be discarded instead of forwarded. Accordingly, the counter increment instruction is changed. A delayed counter increment will perform the actual counter update after the processing of the data packet is completed. In one embodiment of the invention, the counter update action is modified depending upon whether the data packet is forwarded or discarded, and a different counter is selected to be updated. This solves a problem that sometimes the forwarding code is unable to determine if some independent action may later discard a data packet.

Abstract: Methods and systems for detecting and correcting computer software problems that cause an application program to crash upon startup are provided. Unsafe startup actions that are costly to initiate in terms of processor time and memory are handled by placing an unsafe startup action marker into the system registry prior to attempting startup. If an unsafe program module starts or boots successfully without causing the software application to crash, the unsafe startup action marker is deleted from the system registry. If loading the unsafe program module causes the application to crash, then startup actions, including corrective actions, are written into the unsafe startup action marker and are used on subsequent startup of the crashed application program to instruct the application on how to fix the problem. Other unsafe startup actions that are not costly in terms of processor time and memory are initially handled by an exception handler.

Abstract: An apparatus for performing phase-lock in a field programmable gate array includes a phase detector configured to determine a phase difference between a carry logic oscillator signal and a reference clock signal; and a combinational circuit coupled to the phase detector, and adapted to function as a variable carry logic oscillator, and further configured to generate the carry logic oscillator signal. A method for performing phase-lock in a field programmable gate array includes: using a carry logic oscillator in a field programmable gate array to generate a carry logic oscillator signal; and determining a phase difference between the carry logic oscillator signal and a reference clock signal.

Abstract: The basic idea comprised of the present invention is to decentralize the generation of time information without suffering from the cost disadvantages expectable due to use of prior art techniques necessary for synchronizing and correcting a plurality instead of only one or two of time suppliers caused by said decentralization. This is achieved by the approach not to readjust the oscillator(s), but, instead, to accept the inaccuracy of the physical device ‘oscillator’ but to measure its inaccuracy and to correct it with the aid of a continuos correction calculation which is advantageously done in a digital way under usage of ETS input information and system oscillator output information.

Abstract: A method and structure for counting and storing the number of occurrences of each of a plurality of events occurring in a processor complex, which processor complex has at least one processor which processes multiple groups of data in a multiplicity of ways, is provided. The structure includes multiple storage devices, each of which includes a plurality of arrays of memory storage for storing count information of each event, which arrays are divided into a plurality of separately addressable groups of memory addresses in each memory array. At least one counter element is associated with each array of memory. A table is provided which contains information, including a point of reference in each array to uniquely define the structure and location of each memory array. At least one processor generates a plurality of parameters for each of the events to uniquely identify the event.

Abstract: A multi-stage clock distribution scheme for use in a signaling server organized into a plurality of uniquely addressable shelves. The signaling server includes a system timing generator, one or more clock distribution modules arranged in a nested hierarchical manner, and a plurality of bus control modules, wherein each bus control module interfaces with at least a portion of line cards disposed in a shelf. The system timing generator provides a framed serial control signal, SFI, for controlling the operation of the multi-stage clock distribution scheme. The SFI signal encodes the IDs of the clock distribution modules and bus control modules whereby a system clock generated by the system timing generator based on a select reference input is successively fanned-out by the intermediate clock distribution modules based on address and ID information encoded in select fields of the SFI frames until the fanned-out system clocks are received by the bus control modules.

Abstract: A phase error measurement circuit for measuring phase error between two clocks on an integrated circuit is provided. The measurement circuit includes first and second clock signal inputs, a phase lead detector, a phase lag detector and a phase error measurement output. The phase lead detector includes a phase lead latch having a data input, which is coupled to the first clock signal input, a latch control input, which is coupled to the second clock signal input and a data output. The phase lag detector includes a phase lag latch having a data input, which is coupled to the second clock signal input, a latch control input, which is coupled to the first clock signal input and a data output. The phase error measurement output is formed by the data outputs of the phase lead latch and the phase lag latch.

Abstract: A system and method for observing the two clocking phase signals, finding a point in time when said signals have a phase coincidence which is good enough for fulfilling a phase difference requirement (e.g. 20 ps), and switching from one clock source to the other. The essential idea is not to compare the phases directly but to generate an auxiliary signal out of the two clock signals which is easier to handle in order to find that desired point in time and which reflects all desired properties of the time dependent phase shift between said clock signals. At a predetermined location in the cycle of both clock signals (e.g. its positive transition) a pulse is generated out of each of the clock signals with matched identical delay elements located very close to each other on the same chip for both signals. As they match they produce exactly the same pulse widths. The absolute length of the pulse width is of minor relevance as long as the length of the pulses is the same within close limits.

Abstract: A high-speed pipeline device includes n data path circuits connected in cascade between an input terminal and an output terminal. N data passing circuits have transmission times {T1, . . . , Tn} each less than a period P of a reference clock signal, at least one of the transmission times differing from another. N pipe registers connect to the input terminals of the data path circuits to latch data passed from a previous stage or the input terminal. A control signal generating circuit produces n pipeline control signals in response to the reference clock signal. N−1 of the pipeline control signals are generated in cascade from preceding pipeline control signals, and an (n)th pipeline control signal is generated directly from the reference clock signal. The control signal generating circuit provides the n pipeline control signals to the n pipe register, so that the total transmission time from the input terminals to the output terminals is minimal.

Abstract: A logic circuit is disclosed having a digital divider that is capable of generating an intermediate signal in response to an input digital clock signal having a 50% duty cycle, where the intermediate signal has a non-50% duty cycle. First and second output signals are generated by a digital delay circuit in response to the intermediate signal. In the digital delay circuit, the first output signal is delayed by an odd number of substantially identical inverter delays, while the second output signal is delayed by an even number of inverter delays. Such a circuit helps reduce and perhaps minimize the sensitivity of the relative phase difference between the output signals to variations in temperature, supply voltage, and fabrication process parameters.

Abstract: A method and apparatus for protecting a computer system. Specifically, a method and system for validating portions of memory at each power-on cycle is described. A Boot Block is used to validate the BIOS, CMOS and NVRAM of a system. The BIOS may also be used to validate the Boot Block, CMOS and NVRAM.

Abstract: The invention provides a method of automatically overclocking CPUs for a computer system by using a frequency generator with functions of tuning frequency and monitoring, and applying a numeric method to get the frequency for booting a computer system. When a computer system is powered on and enters the overclocking process, the built-in parameters storing booting settings are loaded and backed up to be referenced in the next trial of booting. The frequency of overclocking is calculated by a numeric method according to the highest frequency generated by the frequency generator and the frequency of front side bus of the system. The built-in parameters are then stored to boot up a computer system at next time. Once the configuration of the computer system is changed, the values of parameters are invalid and need to be recalculated by entering the overclocking process. Using this automatic method, overclocking can be done in a shorter time than overclocking manually.

Abstract: A computer peripheral device is prevented from being in power save mode by either forcing the peripheral device out of power save mode or preventing the peripheral device from entering power save mode. A timing mechanism tracks time. The timing mechanism either tracks the time of day, the day of the week, an elapsed time, or a combination of these times. The time tracked by the timing mechanism is compared to a pre-set condition stored in a storage device. If the time meets the pre-set condition, the computer peripheral device is prevented from being in power save mode. The computer peripheral device is prevented from being in power save mode by either transmitting a job to the peripheral device for processing, accessing the control means of the peripheral device and terminating the power save mode, or temporarily disabling the power save mode for the peripheral device.

Abstract: A system and method are provided for counting a number of clock cycles. In one embodiment, the system comprises a cascaded series of write latches and a cascaded series of erase latches. The output of each of the write latches is electrically coupled to a respective diverting multiplexer configured to divert a counting signal from the cascaded series of write latches to the cascaded series of erase latches. In order to count a specific number of cycles of the clock, one of the diverting multiplexers is set so as to divert a logical “1” advancing along the write latches into the erase latches. A specific number of clock cycles is counted by forcing a logical “1” to advance through a predetermined number of write and erase latches. Generally, the number of write and erase latches used to count a given number of clock cycles is even. Consequently, the present invention also includes an odd latch to enable the counting of an odd number of clock cycles.

Abstract: A system is provided to transfer parallel incoming data from an interface device with an external timing domain, for reading in an internal timing domain, without the use of external control signals. System constraints are reduced by permitting an infinite delay to occur in the byte clock timing through the interface device. The system tolerates a specified drift of the byte clock after initialization which may be the result of thermal changes in the interface device, for example. If the specified drift is exceeded, the system is able to reinitialize timing to reestablish the specified byte clock drift, and so continue the transfer of data from the interface device. A method of transferring data using an internal timing domain, from an interface device having an external timing domain, is also provided.

Abstract: In a multiprocessor system, each processor system comprises a first storage means for storing the number of a failing processor among the processors in the processor system, a first notice acceptance means for accepting a notice of the number of a failing processor in another processor and writing the failing processor number to the first storage means, a second notice acceptance means for accepting a notice of initialization from another processor system to initialize own processor, and a notice means for issuing the notice of the initialization to all other processors. The multiprocessor system further comprises a system control processor analysis means for determining the system control processor from among the normally operating processors and a system restart control means for determining whether to perform system restart and, if own processor matches the system control processor, performing the initialization.

Abstract: A method of providing a programmer with a visualization of power usage. The method is especially suitable for integration within a debugging process (FIG. 20). A windows-type display (160, 170, 180, 190) displays sections of computer code (160a, 170a), as well as numerical values representing power usage (160b, 170b). Next to each section of code, some sort of visual representation of power usage is displayed, such as a bar of a bar graph (160c, 170c). Alternatively, the code can be highlighted if power usage exceeds a given threshold, or comments can be provided next to the code for optimizing power usage.

Abstract: An apparatus for producing one or more clock signals comprises a plurality of delay elements sequentially connected and logic circuitry connected to several of the plurality of delay elements. A clock signal fed through the plurality of delay elements produces multiple delayed versions of the clock signal. Logic circuitry selects and combines the delayed clock signal versions to produce one or more output clock signals, each having a frequency that is a selected fraction of the input clock signal. An associated method delays the input clock signal N times sequentially for a natural number N. then selects a series of time splices of the delayed clock signals to produce an output clock signal. In some implementations the input clock signal can be referenced to a reference clock signal. The output clock signal frequency can be set to (N/M)×fref, for a natural number M and reference clock signal frequency fref.