Abstract: A cache has an address bus for receiving requests for data from a processor and a data bus for providing the requested data to the processor. As part of the mechanism for determining if there is a hit in the cache, the cache has TAG locations for storing TAG addresses. The hit signal is not generated unless a TAG address corresponds to the address received on the address bus. Associated with each TAG location are valid bits, disable bits, and LRU bits. The requested data is contained in data locations in the cache. Each data location has a corresponding TAG location. The disable bits can be set under the control of the processor for the case where a data location is defective. Additionally, in various diagnostic modes, the TAG locations, the valid bits, the LRU bits, and the data locations are directly accessible via the data bus.