Abstract: The disclosure relates to a synchronization device that includes two parallel memory areas, a unit for determination of write states that depends on the phase deviation between the input video signal and the synchronization signal, a write management unit that determines, when it receives a write image pulse, the memory (or memories) to be used for the next write depending on the write state and the memory that is currently being read. The two memories are read sequentially and alternately, whereas the memory(ies) used for each write is variable and determined automatically. The invention enables video signals to be synchronized with respect to a synchronization signal with a frequency deviation tolerance of up to 33%.