Patents Examined by Michael S. Lebentratt
  • Method of producing a memory cell configuration
    Patent number: 6180458
    Abstract: A memory cell configuration includes first memory cells with planar MOS transistors and second memory cells with vertical MOS transistors. The planar MOS transistors are disposed on the bottom of and on the crown of parallel, strip-like trenches. The vertical MOS transistors are disposed on the side walls of the trenches. The memory cell configuration can be produced with a mean area requirement for each memory cell of 1 F2, where F is the minimum structure size.
    Type: Grant
    Filed: June 10, 1998
    Date of Patent: January 30, 2001
    Assignee: Infineon Technologies AG
    Inventors: Wolfgang Krautschneider, Franz Hofmann, Wolfgang Roesner