Abstract: A table translator circuit arrangement comprises a plurality of random access word organized memories, input circuitry, output circuitry, and control circuitry. The word locations of each memory are separated into control and data locations defined by corresponding ranges of memory access addresses. Each table entry comprises one or more access control bits and associated data. Each table address defines a control location in one memory of the plurality and data locations in additional memories of the plurality. An entry to be written into the table is provided to input rotate circuitry which is controlled by a portion of the table address which defines the location at which the entry is to be written. The input rotate circuitry delivers the access control bits of the entry to a memory in which a control location is accessed and delivers the associated data bits to additional memories in which data locations are accessed.