Abstract: A matrix calculating circuit for calculating with respect to a matrix in which all diagonal elements are equal to one another and the remaining elements are equal to one another. The matrix calculating circuit includes a register for successively latching "n" items of data that are time-sequentially inputted thereto, a delay circuit for delaying the data supplied from the register by "n" clocks, a total-sum calculating unit for calculating a total sum of the "n" items of data supplied from the register, a data latch for latching a value of the total-sum calculating unit, and an adder for adding output data of the delay circuit to output data of the data latch. The "n" items of data to be latched by the register may be supplied from an output portion of an image sensor, to remove the influence due to the crosstalk.